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PDF CY8C21334B Data sheet ( Hoja de datos )
| Número de pieza | CY8C21334B | |
| Descripción | Programmable System-on-Chip CapSense Controller | |
| Fabricantes | Cypress Semiconductor | |
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CY8C21x34B
PSoC® Programmable System-on-Chip™ CapSense®
Controller with SmartSense™ Auto-tuning
1–21 Buttons, 0–4 Sliders, Proximity
PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity
Features
■ Advanced CapSense® block with SmartSense™ Auto-Tuning
❐ Patented CSD sensing algorithm
❐ SmartSense_EMC Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process
■ Driven shield
❐ Delivers best-in class water tolerant designs
❐ Robust proximity sensing in the presence of metal objects
❐ Supports longer trace lengths
■ Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Industrial temperature range: -40 °C to 85 °C
■ Advanced peripherals (PSoC® blocks)
❐ Four analog Type E PSoC blocks provide:
• Two comparators with digital-to-analog converter (DAC)
references
• Single or dual 10-bit 28 channel analog-to-digital
converters (ADC)
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART), serial peripheral interface (SPI) master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐ Implement a combination up to 21 buttons or 4 sliders using
4 analog blocks and 3 digital blocks
❐ Complex peripherals by combining blocks
■ Flexible on-chip memory
❐ 8-KB Flash /512-B SRAM
❐ 50,000 erase/write cycles
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128-KB trace memory
■ Precision, programmable clocking
❐ Internal ±2.5% 24- / 48-MHz main oscillator[1]
❐ Internal oscillator for watchdog and sleep
■ Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high-Z, strong, or open-drain drive modes
on all GPIOs
❐ Up to eight analog inputs on GPIOs
❐ Configurable interrupt on all GPIOs
■ Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
❐ Capacitive sensing application capability
■ Additional system resources
❐ I2C[2] master, slave, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■ Package options
❐ 16-pin SOIC
❐ 20-pin, 28-pin, 56-pin SSOP
❐ 32-pin QFN
Errata: For information on silicon errata, see “Errata” on page 48. Details include trigger conditions, devices affected, and proposed workaround.
Notes
1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.
2. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep
mode.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-67345 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 3, 2017
1 page  
CY8C21x34B
PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
The PSoC architecture, shown in Figure 2, consists of four main
areas: the core, the system resources, the digital system, and
the analog system. Configurable global bus resources allow
combining all of the device resources into a complete custom
system. Each CY8C21x34B PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 GPIOs are also included. The GPIOs provide
access to the global digital and analog interconnects.
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low speed oscillator (ILO). The CPU
core, called the M8C, is a powerful processor with speeds up to
24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System resources provide these additional capabilities:
■ Digital clocks for increased flexibility
■ I2C functionality to implement an I2C master and slave
■ An internal voltage reference, multi-master, that provides an
absolute value of 1.3 V to a number of PSoC subsystems
■ A SMP that generates normal operating voltages from a single
battery cell
■ Various system resets supported by the M8C
The digital system consists of an array of digital PSoC blocks that
may be configured into any number of digital peripherals. The
digital blocks are connected to the GPIOs through a series of
global buses. These buses can route any signal to any pin,
freeing designs from the constraints of a fixed peripheral
controller.
The analog system consists of four analog PSoC blocks,
supporting comparators, and analog-to-digital conversion up to
10 bits of precision.
The Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that is used alone or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■ PWMs (8- to 32-bit)
■ PWMs with dead band (8- to 32-bit)
■ Counters (8- to 32-bit)
■ Timers (8- to 32-bit)
■ UART 8- with selectable parity
■ Serial peripheral interface (SPI) master and slave
■ I2C slave and multi-master
■ CRC/generator (8-bit)
■ IrDA
■ PRS generators (8-bit to 32-bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 7.
Figure 2. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital Clocks To System Bus
From Core
To Analog
System
8
8
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
DBB00 DBB01 DCB02 DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
8
8
Document Number: 001-67345 Rev. *G
Page 5 of 52
5 Page 
20-pin Part Pinout
Figure 5. CY8C21334B 20-pin PSoC Device
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
VSS
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
SSOP
20 VDD
19 P0[6], A, I, M
18 P0[4], A, I, M
17 P0[2], A, I, M
16 P0[0], A, I, M
15 XRES
14 P1[6], M
13 P1[4], EXTCLK, M
12 P1[2], M
11 P1[0], I2C SDA, M
Table 3. Pin Definitions – CY8C21334B 20-pin (SSOP)
Type
Pin No.
Digital
Analog
Name
Description
1 I/O I, M
P0[7] Analog column mux input
2 I/O I, M
P0[5] Analog column mux input
3 I/O I, M
P0[3] Analog column mux input, integrating input
4 I/O I, M
P0[1] Analog column mux input, integrating input
5 Power
6 I/O M
7 I/O M
VSS
P1[7]
P1[5]
Ground connection
I2C SCL
I2C SDA
8 I/O M
9 I/O M
P1[3]
P1[1]
I2C SCL, ISSP-SCLK[6]
10 Power
11 I/O
M
VSS
P1[0]
Ground connection.
I2C SDA, ISSP-SDATA[6]
12 I/O
M
P1[2]
13 I/O
M
P1[4] Optional external clock input (EXTCLK)
14 I/O
M
P1[6]
15 Input
XRES Active high external reset with internal pull-down
16 I/O
I, M
P0[0] Analog column mux input
17 I/O
I, M
P0[2] Analog column mux input
18 I/O
I, M
P0[4] Analog column mux input
19 I/O
I, M
P0[6] Analog column mux input
20 Power
VDD Supply voltage
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
CY8C21x34B
Note
6. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 001-67345 Rev. *G
Page 11 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C21334B.PDF ] | |
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