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CYWB0164BB 데이터시트 PDF




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부품번호 CYWB0164BB 기능
기능 USB and Mass Storage Controller
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CYWB0164BB 데이터시트, 핀배열, 회로
CYWB0163BB/CYWB0164BB
West Bridge® Bay™ USB and Mass
Storage Controller
Features
Best-in-class sideloading performance (>30 MBps) based on
Cypress's proprietary SLIM® II technology, enabling direct path
from Hi-Speed USB 2.0 to mass storage devices
USB-IF compliance certified
USB 2.0 peripheral
High-Speed On-The-Go (HS-OTG) 2.0 host negotiation pro-
tocol (HNP) and session request protocol (SRP)
Thirty-two endpoints
Integrated USB 2.0 transceivers
EZ-Dtect™ – USB charger detection 1.1
Accessory charger adaptor (ACA)
Integrated Hi-Speed USB 2.0 switch[1]
Carkit Pass-Through UART functionality on USB
Mass storage support
SD 3.0 (SDXC) UHS-1
eMMC 4.4
System I/O expansion with two secure digital I/O (SDIO) ports
Native mass storage class (MSC), human interface device
(HID), full, and Turbo-MTPTM support
Flexible host processor interface
Asynchronous non-multiplexed SRAM
Synchronous and asynchronous address/data multiplexed
SRAM
Multimedia card (MMC) slave with eMMC 4.3/4.4
pass-through boot
Direct memory access (DMA) slave support over processor
interfaces
Ultra low-power in core power-down mode
Less than 60 µA with VBATT on and 20 µA with VBATT off
Independent and flexible power domains
Flexible serial peripheral interfaces (SPIs)
I2C master controller at 1 MHz
I2S master (transmitter only) with sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
UART at 4 Mbps
SPI master at 33 MHz
Selectable clocking frequencies
19.2-, 26-, 38.4-, and 52-MHz clock input
19.2-MHz crystal input
32-kHz low-power clock for watchdog timer
Package options:
5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small
footprint wafer-level chip scale package (WLCSP)
10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
Pin compatible with West Bridge® Benicia™ enabling easy
migration to USB 3.0
Applications
Mobile phones
Portable media players
Portable navigation devices
Personal digital assistant devices
Digital still/video cameras
Note
1. Available only with the WLCSP package.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-45550 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 21, 2014




CYWB0164BB pdf, 반도체, 판매, 대치품
CYWB0163BB/CYWB0164BB
Functional Overview
West Bridge Bay™ is a Hi-Speed USB 2.0 West Bridge
peripheral controller optimized for all sideloading and streaming
applications. It supports the latest removable and embedded
mass-storage devices. The SLIM II architecture, supervised by
the ARM9 CPU core, enables simultaneous accesses among all
the functional Bay ports without affecting the performance of
each independent data path. The functional ports are as follows:
USB port (U-Port) supporting USB 2.0 peripheral and USB 2.0
OTG host
Mass storage port (S-Port) supporting two independent mass
storage devices
Processor port (P-Port) connecting to a host processor
Low-performance peripheral port (LPP-Port) providing
additional serial interfaces
Bay offers the following advantages:
USB host (that is, PC) accessing mass storage attached to Bay
(U-Port S-Port access) in a sideloading application. Bay acts
as a USB 2.0 peripheral
USB host exchanging data with the P-Port host processor
(P-Port U-Port access) in a video streaming or tethered
modem application. Bay acts as a USB 2.0 peripheral
P-Port host processor accessing mass storage or I/O devices
attached to Bay (P-Port S-Port access). Bay acts as a mass
storage bridge
P-Port host processor connecting to mass storage or HID
attached to Bay's USB port (P-Port U-Port access). Bay acts
as a USB 2.0 OTG host
Each of these access paths can operate independently or
simultaneously in an interleaved manner. Bay also supports the
USB composite device driver, enabling simultaneous
enumeration of multiple independent USB device classes.
Interface Description
USB Interface (U-Port)
Bay supports USB peripheral functionality compliant with the
USB 2.0 Specification.
Bay is compliant with the USB OTG supplement revision 2.0.
It supports high-speed, full-speed, and low-speed OTG
dual-role device capability. As a peripheral, it is capable of
high-speed and full-speed.As a host, it is capable of
high-speed, full-speed, and low-speed
Bay supports the Carkit Pass-Through UART functionality on
USB D+/D– lines based on the CEA-936A specification
Bay supports up to 32 endpoints with fully configurable buffer
sizes.
As a USB peripheral, Bay natively supports MSC and Media
Transfer Protocol (MTP) USB peripheral classes. All other
device classes are supported in pass-through mode. The
external host processor, connected to the P-Port, handles
enumeration.
As a USB OTG host, Bay natively supports MSC and HID device
classes. All other device classes can be supported with custom
firmware. Contact Cypress applications support for details.
When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
The Cypress Vendor ID 0X04B4 is the default VID used for
enumeration. This may be changed through firmware.
Figure 1. U-Port Interface Signals
West Bridge
Charger
Bay
detect
VBATT
VBUS
OTG_ID
D-
D+
USB Switch
Bay integrates a high-speed USB 2.0 switch that allows a single
USB connector to be shared with another device. The firmware
can enable or disable this switch. When the switch is enabled,
the USB D+/D– are connected to an external high-speed
USB 2.0 PHY. After power-on-reset (POR) in the normal mode
of operation, the USB switch is enabled by default. Note that this
USB switch is only available with the WLCSP package, not with
the BGA package.
Carkit UART Mode
The U-Port supports the Carkit UART mode (UART over D+/D–)
for non-USB serial data transfer. This complies with the
CEA-936A specification.
In the Carkit UART mode, the output signaling voltage is 3.3 V.
The TXD of UART (output) is mapped to the D– line and the RXD
of UART (input) is mapped to the D+ line.
Bay disables the USB transceiver and the D+ and D– pins
function as pass-through pins to connect to the host processor
UART. When the P-Port is configured to be in the asynchronous
ADMux and PMMC modes, the Carkit UART signals are routed
to the P-Port. In the asynchronous SRAM and synchronous
ADMux modes, the Carkit UART signals are routed to S1-Port
GPIOs as shown in Figure 2. Bay supports a baud rate of up to
9600 bps in this mode.
Document Number: 001-45550 Rev. *J
Page 4 of 52

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CYWB0164BB 전자부품, 판매, 대치품
CYWB0163BB/CYWB0164BB
Table 1. Charger Detect Messages
I2C to PMIC or External Processor
Message 1
Message 2
Message 3
Message 4
Message 5
Message 6
Message 7
Description
Fail negotiation
100 mA available – Host only
500 mA available – Host only
1.8 A available – Wall charger
1.5 A available – Host/hub charger in FS mode
900 mA available – Host/hub charger in HS mode
1.5 A available – Host/hub charger
Note: Other messages can be customized in firmware.
VBUS Overvoltage Protection
Bay can withstand up to 6 V on the VBUS pin. In various failure
scenarios, a charger may supply up to 12 V on VBUS. In this
case, an external overvoltage protection (OVP) device prevents
the failing charger from causing damage to the Bay device.
Figure 4 shows the system application diagram with an OVP
device connected to VBUS. Bay is able to draw power from either
the VBATT or VBUS voltage sources. Therefore, it is also
possible to leave VBUS unconnected in the system and solely
use VBATT as the power source. VBATT can be connected to
the system battery or a stable 3.2–6-V voltage rail from the PMIC.
In this case, Bay does not perform the charger detection function
and this function is supported by the external PMIC. Refer to the
DC Specifications for the operating range of VBUS and VBATT.
Figure 4. System Diagram with OVP Device For VBUS
PMIC
CHG_DET
VBATT
OVP device
VBUS
OTG_ID
D-
D+
West Bridge
Bay
On-The-Go (OTG)
The West Bridge Bay OTG performs the following functions:
Complies with OTG revision 2.0 specification
Supports both A and B device modes and supports control,
interrupt, bulk, and isochronous data transfers
Requires an external charge pump (either standalone or
integrated with a PMIC) to power VBUS in OTG A-device mode
The target peripheral list for OTG host implementation consists
of MSC- and HID-class devices. Other devices may be
supported with custom firmware. Contact Cypress Applications
Support for details
Bay does not support the attach detection protocol (ADP)
OTG Connectivity
In the OTG mode, Bay can be configured to be an A-, B-, or
dual-role device. It can connect to the following:
Targeted USB peripheral
SRP-capable USB peripheral
HNP-capable USB peripheral
OTG host
HNP-capable host
OTG device
The Bay device supports ACA.
GND
Document Number: 001-45550 Rev. *J
Page 7 of 52

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CYWB0164BB

USB and Mass Storage Controller

Cypress Semiconductor
Cypress Semiconductor

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