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CYWB0220ABS 데이터시트 PDF




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부품번호 CYWB0220ABS 기능
기능 USB and Mass Storage Peripheral Controller
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CYWB0220ABS 데이터시트, 핀배열, 회로
CYWB022XX Family
West Bridge®: Astoria™
USB and Mass Storage Peripheral Controller
West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller
Features
Multimedia device support
Up to two SD, SDIO, MMC, MMC+, and CE-ATA devices
Supports Microsoft® Media Transfer Protocol (MTP) with
optimized data throughput
Simultaneous Link to Independent Multimedia (SLIM®)
architecture, enabling simultaneous and independent data
paths between the processor and USB, and between the USB
and mass storage
High-speed USB at 480 Mbps
USB 2.0 compliant
Integrated USB switch
Integrated USB 2.0 transceiver, smart serial interface engine
16 programmable endpoints
GPIF (General Programmable Interface)
Allows direct connection to most parallel interface
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
Flexible processor interface that supports:
Multiplexing and nonmultiplexing address and data interface
SRAM interface
Pseudo cellular random access memory (CRAM) interface
(Antioch interface)
Pseudo NAND flash interface
Logic Block Diagram
SPI (slave mode) interface
Direct memory access (DMA) slave support
FlexBoot
Processor can boot from the processor interface port
Ultra low power, 1.8-V core operation
Low power modes
Small footprint:
3.91 × 3.91 × 0.55 mm 81-ball WLCSP (SP and Lite SP)
6 × 6 × 1.0 mm 100-ball VFBGA
10 × 10 × 1.20 mm 121-ball FBGA
Supports USB Boot, I2C Boot and Processor Boot
Selectable clock input frequencies
19.2 MHz, 24 MHz, 26 MHz, and 48 MHz
Applications
Cellular phones
Portable media players
Personal digital assistants
Portable navigation devices
Digital cameras
POS terminals
Portable video recorders
Data cards and wireless dongles
West BridgeTM AstoriaTM
Control
Registers
uC
Access Control
P
SLIMTM
U
SD/SDIO/
Cypress
MMC+/ CE- N-XpressTM
ATA Block Engine
Configurable Storage
Interface
S
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-13805 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 1, 2014




CYWB0220ABS pdf, 반도체, 판매, 대치품
CYWB022XX Family
The Astoria USB interface supports programmable
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Astoria also has an integrated USB switch (see Figure 1) that
allows interfacing to an external full speed USB PHY.
Figure 1. U-Port With Switch and Control Block
SWD+
UVALID
USBALLO
SWD-
USB 2.0
XCVR
USB Switch
and Control
Block
USB Port D+
(U Port) D-
Mass Storage Support (S-Port)
The S-Port is configurable in five different interface modes:
Simultaneously supporting an SD/SDIO/MMC+/CE-ATA port
and an GPIF
Supporting two SD/SDIO/MMC+/CE-ATA ports
Supporting SD/SDIO/MMC+/CE-ATA port and GPIO
Supporting GPIF and GPIO
Supporting GPIO
These configurations are controlled by the 8051 firmware.
S-Port Configuration Modes
The S Port is configurable in six different interface modes:
GPIF and SD/SDIO/MMC/CE-ATA interface mode
Dual SD/SDIO/MMC/CE-ATA interface mode
SD/SDIO/MMC/CE-ATA and GPIO interlace mode
GPIF and GPIO interface mode
GPIO interface mode
GPIF and SD/SDIO/MMC/CE-ATA Interface Mode
This mode configures the S-Port into GPIF and
SD/SDIO/MMC/MMC+/CE-ATA ports as shown in Figure 2. The
SD/SDIO/MMC/MMC+/CE-ATA port supports either SD, SDIO,
MMC, MMC+, or CE-ATA device.
Figure 2. GPIF and SD/SDIO/MMC/CE-ATA Interface Mode
Dual SD/SDIO/MMC/CE-ATA Interface Mode
The dual SD/SDIO/MMC/MMC+/CE-ATA interface mode
configures the S-Port for up to two
SD/SDIO/MMC/MMC+/CE-ATA port as shown in Figure 3. Each
SD/SDIO/MMC/MMC+/CE-ATA port is independent and
supports different SD, SDIO, MMC, MMC+, or CE-ATA devices.
Figure 3. Dual SD/SDIO/MMC/CE-ATA Interface Mode
SD
SDIO
MMC
MMC+
CE-ATA
Astoria
S Port
OR OR
OR OR
OR OR
OR OR
SD
SDIO
MMC
MMC+
CE-ATA
SD/SDIO/MMC/CE-ATA and GPIO Interface
The SD/SDIO/MMC/MMC+/CE-ATA and GPIO interface mode
configures the S-Port to support SD/SDIO/MMC/MMC+/CE-ATA
device and GPIOs as shown in Figure 4. Each GPIO is
configured as either input or output independently. The
processor accesses those GPIO through the P-Port driver’s API.
Figure 4. SD/SDIO/MMC/CE-ATA and GPIO Interface Mode
GPIO
Astoria
S Port
OR
OR
OR
OR
SD
SDIO
MMC
MMC+
CE-ATA
Document Number: 001-13805 Rev. *O
Page 4 of 78

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CYWB0220ABS 전자부품, 판매, 대치품
CYWB022XX Family
Figure 8. Astoria Power Supply Domains
*VDDQ
VDD
UVDDQ
I/O D-CORE
USB-IO
D+
D-
Power Supply Sequence
The power supplies are independently sequenced without
damaging the part. All power supplies must be up and stable
before the device operates. If the supplies are not stable, the
remaining domains are in low power (standby) state.
Power Modes
In addition to the normal operating mode, Astoria contains
several low power states when normal operation is not required.
Normal Mode
Normal mode is the mode in which Astoria is fully functional. In
this mode, data transfer functions described in this document are
performed.
Suspend Mode
This mode is entered internally by 8051 (the external processor
only initiates entry into this mode through Mailbox commands).
This mode is exited by the D+ bus going low, GPIO[0] going to a
pre-determined state or by asserting CE# LOW.
In Astoria’s suspend mode:
The clocks are shut off
All I/Os maintain their previous state
Core power supply must be retained
The states of the configuration registers, endpoint buffers, and
the program RAM are maintained. All transactions must be
complete before Astoria enters suspend mode (state of
outstanding transactions are not preserved)
The firmware resumes its operation from where it was
suspended because the program counter is not reset
Only inputs that are sensed are RESET#, GPIO[0]/SD_CD,
GPIO[1]/SD2_CD, SD_D3, SD2_D3, D+, and CE#. The last
three are wake up sources (each can be individually enabled
or disabled)
Hard Reset can be performed by asserting the RESET# input,
and Astoria is initialized
Standby Mode
Standby mode is a low-power state. This is the lowest power
mode of Astoria while still maintaining external supply levels.
This mode is entered through the deassertion of the WAKEUP
input pin or through internal register settings. To leave this mode,
assert the WAKEUP, CE#, and RESET#; change state of
GPIO[0]/SD_CD, GPIO[1]/SD2_CD, SD_D3, and SD2_D3.
In this mode all configuration register settings and program RAM
contents are preserved. However, data in the buffers or other
parts of the data path, if any, is not guaranteed in values.
Therefore, the external processor must ensure that the required
data is read before placing Astoria in the standby mode.
In the standby mode:
The program counter is reset on waking up from standby mode
All outputs are tristated and I/O is placed in input only
configuration. Values of I/Os in standby mode are listed in the
pin assignments table
Core power supply must be retained
Hard Reset can be performed by asserting the RESET# input,
and Astoria is initialized
PLL is disabled
USB switches the SWD+/SWD– to D+/D–
Core Power Down Mode
The core power supply VDD is powered down in this state.
Because AVDDQ is tied to the same supply as VDD, it is also
powered down. The endpoint buffers, configuration registers,
and program RAM do not maintain state. All VDDQ power
supplies (except AVDDQ) must be ON and not power down in
this mode. VDD33 must also remain ON. It has an option that the
UVDDQ can be powered down or stay ON while VDD is powered
down when SWD+/SWD– are not connected. The UVDDQ
cannot be powered down when SWD+/SWD– is connected, or
VDD is active. When UVDDQ is powered down, D+/D– cannot be
driven by an external device.
In the WLCSP package, AVDDQ is internally tied to XVDDQ.
Due to this, the clock input at XTALIN must be brought to a
steady low level prior to entry into Core Power Down Mode. In
the WLCSP package, VDD33 is tied to UVDDQ internally.
UVDDQ must be ON during the core power down mode
The core power down mode has two power down options:
Core only power down – VDD power down
Core and USB power down – VDD and UVDDQ are both
powered down. In this option, SWD+/SWD– are not connected
and cannot be driven by an external device
In these power down options, the endpoint buffers, configuration
registers, or the program RAM do not maintain state. It is
necessary to reload the firmware on exiting from this mode. All
VDDQ power supplies must be ON and not powered down in this
mode.
In the 82-ball WLCSP package, in the core power down mode,
the USB switches the SWD+/SWD– to D+/D–.
Document Number: 001-13805 Rev. *O
Page 7 of 78

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부품번호상세설명 및 기능제조사
CYWB0220ABS

USB and Mass Storage Peripheral Controller

Cypress Semiconductor
Cypress Semiconductor

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