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Número de pieza | CYUSB3025 | |
Descripción | USB and Mass Storage Peripheral Controller | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CYUSB3025 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! CYUSB302x
SD3™ USB and Mass Storage
Peripheral Controller
Features
■ Latest-generation storage support
❐ SD3.0/SDXC – UHS1 SDR50 / DDR50 Master
❐ eMMC 4.4 Master
❐ SDIO 3.0 Master
■ USB integration
❐ Certified USB 3.0 and USB 2.0 peripheral: SuperSpeed (SS),
Hi-Speed (HS), and Full-Speed (FS) only)
❐ Thirty-two physical endpoints
❐ Integrated transceiver
❐ Accessory charger adaptor (ACA) support
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
■ I2C master controller at 1 MHz
■ Selectable input clock frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Independent power domains for core and I/O
■ 10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
■ 5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small
footprint wafer-level chip scale package (WLCSP)
Logic Block Diagram
Applications
■ USB thumb drives
■ Card readers
■ Laptop with SD slots
■ SD slot in TV/STB
■ WIFI Dongles
■ USB SDIO Bridge
■ Raid on-Chip Controller
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
JTAG
ARM926EJ-S
Embedded
SRAm
(512 kB/
256 KB)
GPIOs
USB
EPs
SS
Peripheral
HS/FS
Peripheral
UART
SPI
I2C I2S
SDIO/SD/MMC Controller
S0-PORT
S1-PORT
SSRX-
SSRX+
SSTX-
SSTX+
D+
D-
Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-55190 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 14, 2016
1 page CYUSB302x
Power
SD3 has the following main groups of power supply domains:
■ IO_VDDQ: This refers to a group of independent supply
domains for digital I/Os. The voltage level on these supplies
are 1.8 V to 3.3 V. SD3 provides six independent supply
domains for digital I/Os listed as follows:
❐ S0VDDQ: S0-Port (for SD/MMC) I/O Power Supply Domain
❐ S1VDDQ: S1-Port (for SD/MMC) I/O Power Supply Domain
❐ S2VDDQ: S2-Port (GPIO) Power Supply Domain
❐ VIO4: S1-Port GPIO[53:57]/O Power Supply Domain (these
pins support MMC’s high nibble data line - D[7:4] on S1-Port)
❐ VIO5: I2C Power Supply Domain (supports 1.2 V to 3.3 V)
❐ CVDDQ: Clock Power Supply Domain
■ VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
❐ AVDD: This is the 1.2-V supply for the PLL, crystal oscillator
and other core analog circuits
❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-
ages for the USB 3.0 interface.
■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through SD3’s internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Power Modes
SD3 supports the following power modes:
■ Normal mode: This is the full-functional operating mode. In this
mode the internal CPU clock and the internal PLLs are enabled.
Normal operating power consumption does not exceed the sum
of ICC_CORE max and ICC_USB max (see Table 9 on page 15
for current consumption specifications).
The I/O power supplies (S0VDDQ, S1VDDQ, VIO4, and VIO5)
may be turned off when the corresponding interface is not in use.
S2VDDQ cannot be turned off at any time if the S2-Port is used
in the application.
■ SD3 supports four low-power modes (see Table 6 on page 5):
❐ Suspend mode with USB 3.0 PHY enabled (L1 mode)
❐ Suspend mode with USB 3.0 PHY disabled (L2 mode)
❐ Standby mode (L3 mode)
❐ Core power-down mode (L4 mode)
Table 6. Entry and Exit Methods for Low-Power Modes
Low Power Mode
Characteristics
Methods of Entry
Methods of Exit
■ The power consumption in this mode does
not exceed ISB1
■ USB 3.0 PHY is enabled and is in U3 mode
(one of the suspend modes defined by the
USB 3.0 specification). This one block alone
operates with its internal clock while all other
clocks are shut down
■ All I/Os maintain their previous state
■ D+ transitioning to low or high
Suspend mode with
USB 3.0 PHY Enabled
(L1 mode)
■
Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off individ-
ually
■
Firmware executing on the core can put
SD3 into suspend mode. For example,
on USB suspend condition, firmware
may decide to put SD3 into suspend
■ D– transitioning to low or high
■ Resume condition on SSRX +/-
■ Detection of VBUS
■ The states of the configuration registers,
buffer memory and all internal RAM are
mode
■ Assertion of GPIO[17]
maintained
■ Assertion of RESET#
■ All transactions must be completed before
SD3 enters Suspend mode (state of
outstanding transactions are not preserved)
■ The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
Document Number: 001-55190 Rev. *J
Page 5 of 32
5 Page CYUSB302x
Pinout for WLCSP
Figure 3. SD3 WLCSP Ball Map (Bottom View)[2]
12
A VSS
B L_GPIO[55]
C L_GPIO[56]
11
VSS
LVDDQ
S1VDDQ
10
SSRXM
SSRXP
U3RXVDDQ
9
R_USB3
U3VSSQ
8
SSTXM
SSTXP
U3TXVDDQ
7
FSLC[ 0 ]
FSLC[ 2 ]
CVDDQ
6
AV SS
XTALIN
CLKIN_32
5
AVDD
XTALOUT
CLKIN
4
DP
SWDP
U 2 PLLV SS
Q
3
U2AFEVSSQ
R_USB2
OTG_ID
2
DM
SWDM
TDO
1
VDD
VDD
TRST#
D S1_GPIO[49] S1_GPIO[50] L_GPIO[53] L_GPIO[54]
RESET#
E L_GPIO[57] S1_GPIO[48] S1_GPIO[51] S1_GPIO[52] I2C_O[60]
F
VSS
S1_GPIO[46] S1_GPIO[47]
FSLC[ 1]
TDI
G S0VDDQ S0_GPIO[43] S0_GPIO[44] S0_GPIO[45]
VSS
VDD
VSS
VDD
VSS
I2 C_ GPIO[ 58 ]
VSS
VDD
VDD
TM S
VSS
VDD
VSS
I2CVDDQ
VSS
VDD
P_ GPIO[ 9 ]
TCK
I2 C_ GPIO[ 59 ]
VSS
P_ GPIO[ 3 ]
P_ GPIO[ 4 ]
P_ GPIO[ 7]
VBATT
P_ GPIO[ 1]
P_ GPIO[ 6 ]
VBUS
P_ GPIO[ 0 ]
P_ GPIO[ 2 ]
H
VSS
S0_GPIO[40] S0_GPIO[41] S0_GPIO[42] S0_GPIO[39]
VSS
P_GPIO[20] P_GPIO[18] P_GPIO[14] P_GPIO[12] P_GPIO[8]
J S0VDDQ S0_GPIO[38] S0_GPIO[37] S0_GPIO[36] P_GPIO[31] P_GPIO[27] P_GPIO[25] P_GPIO[22] P_GPIO[19] P_GPIO[15] P_GPIO[10]
K S0_GPIO[35] S0_GPIO[34] S0_GPIO[33] P_GPIO[32] P_GPIO[28] P_GPIO[26] P_GPIO[16] P_GPIO[21]
INT#
P_GPIO[24] P_GPIO[11]
L VDD
VSS
VDD
P_GPIO[30] P_GPIO[29] PVDDQ P_GPIO[23]
VSS
PVDDQ
P_GPIO[17] P_GPIO[13]
PVDDQ
P_ GPIO[ 5]
VSS
VSS
Note
2. No ball is populated at location A9.
Document Number: 001-55190 Rev. *J
Page 11 of 32
11 Page |
Páginas | Total 30 Páginas | |
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