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PDF HM-6516-883 Data sheet ( Hoja de datos )
| Número de pieza | HM-6516-883 | |
| Descripción | 2K x 8 CMOS RAM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM HM-6516/883
March 1997
2K x 8 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max
• Low Power Operation . . . . . . . . . . . . . .55mW/MHz Max
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC
• TTL Compatible
• Static Memory Cells
• High Output Drive
• On-Chip Address Latches
• Easy Microprocessor Interfacing
The HM-6516/883 is a CMOS 2048 x 8 Static Random
Access Memory. Extremely low power operation is achieved
by the use of complementary MOS design techniques. This
low power is further enhanced by the use of synchronous cir-
cuit techniques that keep the active (operating) power low,
which also gives fast access times. The pinout of the HM-
6516/883 is the popular 24 pin, 8-bit wide JEDEC Standard
which allows easy memory board layouts, flexible enough to
accommodate a variety of PROMs, RAMS, EPROMs, and
ROMs.
The HM-6516/883 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum because only one device is enabled at a time. The
address latches allow very simple interfacing to recent gen-
eration microprocessors which employ a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
Ordering Information
120ns
HM1-6516B/883
HM4-6516B/883
200ns
HM1-6516/883
-
TEMPERATURE RANGE PACKAGE PKG. NO.
-55oC to 125oC
CERDIP F24.6
-55oC to +125oC
CLCC
J32.A
Pinouts
HM-6516/883
(CERDIP)
TOP VIEW
HM-6516/883
(CLCC)
TOP VIEW
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
DQ0 9
DQ1 10
DQ2 11
GND 12
24 VCC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
26 W
A2 9
25 G
A1 10
24 A10
A0 11
23 E
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
PIN DESCRIPTION
NC No Connect
A0 - A10 Address Inputs
E Chip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC Power (+5V)
W Write Enable
G Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
173
FN2999.1
1 page  
HM-6516/883
TABLE 3. HM-6516/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
PARAMETER
Input Capacitance
Input/Output
Capacitance
Chip Enable to Output
Valid Time
Write Enable Output
Disable Time
Chip Enable Output
Disable Time
Output Enable
Access Time
Output Enable to
Output Valid Time
Output Disable Time
SYMBOL
CI
CIO
(3) TELQX
(4) TWLQZ
(5) TEHQZ
(6) TGLQV
(7) TGLQX
(8) TGHQZ
CONDITIONS
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
VCC = 4.5 and 5.5V
VCC = 4.5 and 5.5V
HM-6516/883
VCC = 4.5 and 5.5V
HM-6516B/883
VCC = 4.5 and 5.5V
HM-6516/883
VCC = 4.5 and 5.5V
HM-6516B/883
VCC = 4.5 and 5.5V
VCC = 4.5 and 5.5V
VCC = 4.5 and 5.5V
HM-6516/883
VCC = 4.5 and 5.5V
HM-6516B/883
NOTES
1, 2
TEMPERATURE
TA = +25oC
1, 3 TA = +25oC
1, 2 TA = +25oC
1, 3 TA = +25oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
1 -55oC ≤ TA ≤ +125oC
MIN
-
-
-
-
10
-
-
-
-
-
10
-
-
MAX
8
UNITS
pF
12 pF
10 pF
14 pF
- ns
80 ns
50 ns
80 ns
50 ns
80 ns
- ns
80 ns
50 ns
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
2. Applies to LCC device types only.
3. Applies to DIP device types only.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
177
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| PDF Descargar | [ Datasheet HM-6516-883.PDF ] | |
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