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PDF LTC3735 Data sheet ( Hoja de datos )
| Número de pieza | LTC3735 | |
| Descripción | 2-Phase High Efficiency DC/DC Controller | |
| Fabricantes | Linear | |
| Logotipo |  |
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FEATURES
n Output Stages Operate Antiphase
n ±1% Output Voltage Accuracy
n 6-Bit IMVP-IV VID Code: VOUT = 0.7V to 1.708V
n Intel Compatible Power Saving Mode (PSIB)
n Stage Shedding Improves Low Current Efficiency
n Power Good Output with Adaptive Masking
n Lossless Voltage Positioning
n Dual Input Supply Capability for Load Sharing
n Resistor Programmable VOUT at Boot-Up and Deeper
Sleep State
n Resistor Programmable Deep Sleep Offset
n Programmable Fixed Frequency: 210kHz to 550kHz
n Adjustable Soft-Start Current Ramping
n Foldback Output Current Limit
n Short-Circuit Shutdown Timer with Defeat Option
n Overvoltage Protection
n Available in 36-Lead SSOP (0.209 Wide) and 38-Lead
(5mm × 7mm) Packages
APPLICATIONS
n Mobile and Desktop Computers
n Internet Servers
LTC3735
2-Phase, High Efficiency
DC/DC Controller for
Intel Mobile CPUs
DESCRIPTION
The LTC®3735 is a 2-phase synchronous step-down
switching regulator controller that drives all N-channel
power MOSFETs in a constant frequency architecture. The
output voltage is programmable by six VID bits during
normal operation and by external resistors during initial
boot-up and deeper sleep state. The LTC3735 drives its two
output stages out-of-phase at frequencies up to 550kHz
to minimize the RMS ripple currents in both input and
output capacitors. This antiphase technique also doubles
the apparent switching frequency, improving the transient
response while operating each phase at an optimum fre-
quency for efficiency. Thermal design is further simplified
by cycle-by-cycle current sharing between the two phases.
An Intel compatible PSIB input is provided to select between
two modes of operation. Fully enhanced synchronous
mode achieves a very small output ripple and very fast
transient response while power saving mode realizes
very high efficiency. OPTI-LOOP® compensation allows
the transient response to be optimized for a wide range
of output capacitance and ESR values.
L, LT, LTC, LTM, OPTI-LOOP, PolyPhase, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
100pF
232k
4R.C74k
4C7C0pF
VOA+
4.5V TO 7V
4.7µF
BAT54A
0.1µF
0.47µF
SW2
0.47µF
SW1
MCH_PG
DPRSLPVR
STP_CPUB
PSIB
FREQSET
TG1
SW1
BG1
VID5-VID0 PGND
PGOOD
ITH
SSEENNSSEE11+–
RUN/SS
TG2
SGND
SW2
BG2
LTC3735
PVCC
SSEENNSSEE22+–
RBOOT
BOOST1 RDPRSLP
BOOST2 RDPVSOLAP+
OAVOOUAT–
M1 1µH
M2 D1
M3 1µH
M4 D2
12.7k 13.3k
56.2k
1.27M
13.3k
549k VOA+
3735 F01
0.002Ω
0.002Ω
VOUT
0.7V TO 1.708V
+
COUT 40A
330µF
2V
×5
Figure 1. High Current 2-Phase Step-Down Converter
VIN
5V TO 24V
CIN
10µF
35V
×4
3735fa
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
LTC3735
Active Mode Efficiency
(Figure 14)
100 VID = 1.468V
PSI = 0
VIN = 7.5V
90
VIN = 20V
80
70
60 0
5 10 15 20 25
LOAD CURRENT (A)
30
3735 G01
Supply Current vs PVCC Voltage
and Mode
2500
2000
ON
1500
1000
500
0
4
SHUTDOWN
56
PVCC VOLTAGE (V)
7
3735 G04
Maximum Current Sense
Threshold vs VRUN/SS (Soft-Start)
80 VSENSE(CM) = 1.25V
70
60
50
40
30
20
10
0
012345
VRUN/SS (V)
3735 G07
Deeper Sleep Mode Efficiency
(Figure 14)
90 PSI = 0
80 VIN = 7.5V
VIN = 20V
70
60
0.01
0.1 1
LOAD CURRENT (A)
10
3735 G02
Maximum Current Sense
Threshold vs Duty Factor
75
50
25
0
0 20 40 60 80 100
DUTY FACTOR (%)
3735 G05
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
76
72
68
64
60
01 2 345
COMMON MODE VOLTAGE (V)
3735 G08
Efficiency vs Input Voltage
(Figure 14)
100 IOUT = 20A
VOUT = 1.6V
90
80
70
60
50
5
10 15
INPUT VOLTAGE (V)
20
3735 G03
Maximum Current Sense
Threshold vs Percent of Nominal
Output Voltage (Foldback)
80
70
60
50
40
30
20
10
0
0 25 50 75 100
PERCENT OF NOMINAL OUTPUT VOLTAGE (%)
3735 G06
Current Sense Threshold
vs ITH Voltage
90
80
70
60
50
40
30
20
10
0
–10
–20
–30
0 0.5 1 1.5 2 2.5
VITH (V)
3735 G09
3735fa
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5 Page 
LTC3735
OPERATION (Refer to Functional Diagram)
Output Voltage at Start-Up and at Deeper Sleep State
Under normal conditions, the output voltage of the regula-
tor is commanded by six VID bits, except at start-up and
at deeper sleep state. At start-up, the RUN/SS capacitor
starts to charge up and its voltage limits the inrush current
from the input power source. This linearly rising current
limit provides a controlled output voltage rise. During
start-up, the VID command is ignored and the output set
point is determined by the value of the resistor connected
to the RBOOT pin. The VID bits continue to be ignored for
15 switching cycles after the completion of the following
two conditions: 1) output voltage has risen up and has
regulated 2) MCH_PG signal has asserted. After 15 switch-
ing cycles, output voltage is fully commanded by VID bits.
In deeper sleep state, the VID command and STP_CPUB
signal are ignored and the output set point is determined
by the parallel value of the resistors at the RDPRSLP pin
and RDPSLP pin.
Operational Amplifier and Deep Sleep Offset
The internal operational amplifier provides a programmable
output offset at deep sleep state (when the STP_CPUB
signal is low). The offset percentage is programmed by
the resistor from RDPSLP to
output to VOA+. The amplifier
VOA+ and the resistor from
has an output slew rate of
5V/µs and is capable of driving capacitive loads with an
output RMS current typically up to 40mA. The open-loop
gain of the amplifier is >120dB and the unity-gain band-
width is 2MHz.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good
The PGOOD pin is connected to the drain of an internal
N‑channel MOSFET. The MOSFET turns on when the out-
put voltage is not within ±10% of its nominal set point.
When the output voltage is within ±10% of its nominal set
point, the MOSFET turns off and PGOOD is high imped-
ance. PGOOD monitors the VBOOT voltage when MCH_PG
is not asserted. During VID, deep sleep or deeper sleep
transitions, PGOOD is masked from going low for 110µs,
preventing the system from resetting during CPU mode
changes. When VID bits, STP_CPUB or DPRSLPVR signals
change again after a previous transition, but before the
timer expires, the internal timer resets.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the in-
rush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full-load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit.
If the output voltage falls to less than 70% of its nominal
output voltage the RUN/SS capacitor begins discharg-
ing assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until the
RUN/SS pin voltage is recycled. This built-in latchoff can
be overidden by providing a current >5µA to the RUN/SS
pin. This current shortens the soft-start period but also
prevents net discharge of the RUN/SS capacitor during a
severe overcurrent and/or short-circuit condition. Foldback
current limiting is activated when the output voltage falls
below 70% of its nominal level whether or not the short-
circuit latchoff circuit is enabled.
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11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3735.PDF ] | |
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