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부품번호 S29WS512P 기능
기능 Simultaneous Read/Write Flash
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S29WS512P 데이터시트, 핀배열, 회로
S29WS512P
S29WS256P
S29WS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V,
Simultaneous Read/Write Flash
Features
Single 1.8 V read/program/erase (1.70–1.95 V)
90 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero latency
Random page read access mode of 8 words with 20 ns intra page
access time
32 Word / 64 Byte Write Buffer
Sixteen-bank architecture consisting of
32/16/8 Mwords for 512/256/128P, respectively
Four 16 Kword sectors at both top and bottom of memory array
510/254/126 64Kword sectors (WS512/256/128P)
Programmable linear (8/16/32) with or without wrap around and
continuous burst read modes
Secured Silicon Sector region consisting of 128 words each for
factory and 128 words for customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
Command set compatible with JEDEC (42.4) standard
Hardware (WP#) protection of top and bottom sectors
Dual boot sector configuration (top and bottom)
Handshaking by monitoring RDY
Offered Packages
– WS512P/WS256P/WS128P: 84-ball FBGA
(11.6 mm x 8 mm)
Low VCC write inhibit
Persistent and Password methods of Advanced Sector Protection
Write operation status bits indicate program and erase operation
completion
Suspend and Resume commands for Program and Erase
operations
Unlock Bypass program command to reduce programming time
Synchronous or Asynchronous program operation, independent of
burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
General Description
The Spansion S29WS512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These burst mode
Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using
separate data and address pins. These products can operate up to 104 MHz and use a single VCC of 1.7 V to 1.95 V that makes
them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power
consumption.
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch Access Time (tIACC)
Max. Synch. Burst Access, ns (tBACC)
Max OE# Access Time, ns (tOE)
Max. Asynch. Access Time, ns (tACC)
104
103.8
7.6
7.6
80
Current Consumption (typical values)
Continuous Burst Read @ 104 MHz
Simultaneous Operation 104 MHz
Program
Standby Mode
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (VCC) Per Word
Effective Write Buffer Programming (VACC) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
36 mA
40 mA
20 mA
20 µA
40 µs
9.4 µs
6 µs
350 ms
600 ms
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-01747 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 17, 2015




S29WS512P pdf, 반도체, 판매, 대치품
S29WS512P
S29WS256P
S29WS128P
2. Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Input/Output Descriptions
Symbol
AMAX–A0
DQ15–DQ0
CE#
OE#
WE#
VCC
VCCQ
VSS
NC
RDY
CLK
AVD#
RESET#
WP#
ACC
RFU
Type
Input
I/O
Input
Input
Input
Supply
Supply
Supply
No Connect
Output
Input
Input
Input
Input
Input
Reserved
Description
Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for WS256P, and
22 for WS128P)
Data input/output.
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
Device Power Supply
Device Input/Output Power Supply (Must be ramped simultaneously with VCC)
Ground.
Not connected internally.
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter. Should be at VIL or VIH while in asynchronous mode.
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode, causes
starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at
VIH for all other conditions.
Acceleration Input. At VHH, accelerates programming; automatically places device in unlock bypass
mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
Reserved for future use (see MCP look-ahead pinout for use with MCP).
Document Number: 002-01747 Rev. *A
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S29WS512P 전자부품, 판매, 대치품
S29WS512P
S29WS256P
S29WS128P
Figure 4.2 VBH084—84-ball Fine-Pitch Ball Grid Array, 11.6 x 8 mm MCP Compatible Package
0.05 C D A
(2X)
D1
e
e
E
A1 CORNER
INDEX MARK
10
TOP VIEW
A
A1
SEATING PLANE
SIDE VIEW
B
0.05 C
(2X)
A2
C
ML K J
6
NXφb
φ 0.08 M C
φ 0.15 M C A B
HGF E DCB A
SD 7
0.10 C
BOTTOM VIEW
0.08 C
10
9
87
SE
7
6
E1
5
4
3
2
1
A1 CORNER
PACKAGE
JEDEC
SYMBOL
A
A1
A2
D
E
D1
E1
MD
ME
N
φb
e
SD / SE
VBH 084
N/A
11.60 mm x 8.00 mm NOM
PACKAGE
MIN NOM MAX
--- --- 1.00
0.18
---
---
0.62 --- 0.76
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
10
84
0.33 --- 0.43
0.80 BSC.
0.40 BSC.
(A2-A9, B10-L10,
M2-M9, B1-L1)
NOTE
OVERALL THICKNESS
BALL HEIGHT
BODY THICKNESS
BODY SIZE
BODY SIZE
BALL FOOTPRINT
BALL FOOTPRINT
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
Note:
BSC is an ANSI standard for Basic Space Centering.
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
4.3 MCP Look-ahead Connection Diagram
Spansion Inc. provides this standard look-ahead connection diagram that supports
NOR Flash and SRAM densities up to 4 Gigabits
NOR Flash and pSRAM densities up to 4 Gigabits
NOR Flash and pSRAM and data storage densities up to 4 Gigabits
Document Number: 002-01747 Rev. *A
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