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CY14B116M 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 CY14B116M은 전자 산업 및 응용 분야에서
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PDF 형식의 CY14B116M 자료 제공

부품번호 CY14B116M 기능
기능 16-Mbit (2048 K x 8/1024 K x 16) nvSRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


CY14B116M 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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CY14B116M 데이터시트, 핀배열, 회로
CY14B116K/CY14B116M
16-Mbit (2048 K × 8/1024 K × 16) nvSRAM with
Real Time Clock
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
25-ns and 45-ns access times
Internally organized as 2048 K × 8 (CY14B116K),
1024 K × 16 (CY14B116M)
Hands-off automatic STORE on power-down with only a
small capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Sleep mode operation
Full-featured real time clock (RTC)
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 A (typical)
Low power consumption
Active current of 75 mA at 45 ns
Standby mode current of 750 A
Sleep mode current of 10 A
Operating voltage: VCC = 2.7 V to 3.6 V
Industrial temperature: –40 C to +85 C
Packages
44-pin thin small-outline package (TSOP II)
54-pin thin small-outline package (TSOP II)
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14B116K/CY14B116M combines a 16-Mbit
nvSRAM with a full-featured RTC in a monolithic integrated
circuit. The nvSRAM is a fast SRAM with a nonvolatile element
in each memory cell. The memory is organized as 2048 K bytes
of 8 bits each or 1024 K words of 16 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data residing in the nonvolatile elements do not
change when data is written to the SRAM. Data transfers from
the SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power-down. On power-up, data is
restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL operations
are also available under software control.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high-accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67786 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 7, 2015




CY14B116M pdf, 반도체, 판매, 대치품
CY14B116K/CY14B116M
Pinouts
Figure 1. Pin Diagram: 44-Pin TSOP II (×8)
Figure 2. Pin Diagram: 54-Pin TSOP II (×16)
INT
A20
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
Xout
Xin
1
2
3
4
5
6
7
8
9 44 - TSOP II
10 (x8)
11
12
13
Top View
(not to scale)
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC[5]
A19
A18
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
VCAP
A14
A13
A12
A11
A10
VRTCcap
VRTCbat
INT
A19
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
54 - TSOP II
12 (x16)
13
14 Top View
15 (not to scale)
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
A18
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
VRTCcap
VRTCbat
Figure 3. Pin Diagram: 165-Ball FBGA (×16)
1 2 3 4 5 6 7 8 9 10 11
A
NC A6
A8
WE
BLE
CE1
NC
OE
A5
A3
NC
B
NC
DQ0
DQ1
A4
BHE
CE2
NC
A2
NC NC NC
C
ZZ NC NC VSS A0
A7
A1
VSS
NC
DQ15
DQ14
D NC DQ2 NC VSS VSS VSS VSS VSS Xin NC NC
E
NC VCAP NC
VCC
VSS
VSS
VSS
VCC
Xout
DQ13
NC
F
NC
DQ3
NC
VCC
VCC
VSS
VCC
VCC
NC
NC DQ12
G
HSB
NC
NC
VCC
VCC
VSS
VCC
VCC
NC
NC
NC
H
NC
NC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
NC
NC
J
NC
NC
NC
VCC
VCC
VSS
VCC
VCC
NC
DQ8
NC
K
NC
NC
DQ4
VCC
VCC
VSS
VCC
VCC
NC
NC
NC
L
NC DQ5 NC VCC VSS VSS VSS VCC NC
NC DQ9
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC DQ10 NC
N INT DQ6 DQ7 VSS A11 A10 A9 VSS NC NC NC
P NC NC NC A13 A19 VRTCbat A18 A12 NC DQ11 NC
R
NC
NC
A15
NC
A17 VRTCcap A16
NC[5]
A14
NC
NC
Note
5. Address expansion for the 32-Mbit. NC pin not connected to die.
Document #: 001-67786 Rev. *J
Page 4 of 42

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CY14B116M 전자부품, 판매, 대치품
CY14B116K/CY14B116M
Hardware STORE (HSB) Operation
The CY14B116K/CY14B116M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a Hardware STORE cycle. When the HSB pin is driven
LOW, the device conditionally initiates a STORE operation after
tDELAY. A STORE cycle begins only if a write to the SRAM has
taken place since the last STORE or RECALL cycle. The HSB
pin also acts as an open drain driver (an internal 100-kweak
pull-up resistor) that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation, HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100-kpull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. If the write latch is not set, HSB is not driven LOW
by the device. However, any of the SRAM read and write cycles
are inhibited until HSB is returned HIGH by the host
microcontroller or another external source.
During any STORE operation, regardless of how it is initiated,
the device continues to drive the HSB pin LOW, releasing it only
when the STORE is complete. Upon completion of the STORE
operation, the nvSRAM memory access is inhibited for tLZHSB
time after the HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up, or after any low-power condition
(VCC < VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power-up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. A Software STORE cycle is
initiated by executing sequential CE or OE controlled read cycles
from six specific address locations in exact order. During the
STORE cycle, the previous nonvolatile data is first erased,
followed by a store into the nonvolatile elements. After a STORE
cycle is initiated, further reads and writes are disabled until the
cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence. Otherwise, the sequence is
aborted and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid Read
2. Read address 0xB1C7 Valid Read
3. Read address 0x83E0 Valid Read
4. Read address 0x7C1F Valid Read
5. Read address 0x703F Valid Read
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE-controlled
reads or OE-controlled reads, with WE kept HIGH for all the six
read sequences. After the sixth address in the sequence is
entered, the STORE cycle commences and the chip is disabled.
HSB is driven LOW. After the tSTORE cycle time is fulfilled, the
SRAM is activated again for the read and write operations.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations:
1. Read address 0x4E38 Valid Read
2. Read address 0xB1C7 Valid Read
3. Read address 0x83E0 Valid Read
4. Read address 0x7C1F Valid Read
5. Read address 0x703F Valid Read
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared; then, the nonvolatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
again ready for read and write operations. The RECALL
operation does not alter the data in the nonvolatile elements.
Document #: 001-67786 Rev. *J
Page 7 of 42

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관련 데이터시트

부품번호상세설명 및 기능제조사
CY14B116K

16-Mbit (2048 K x 8/1024 K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B116L

16-Mbit (2048 K x 8/1024 K x 16/512 K x 32) nvSRAM

Cypress Semiconductor
Cypress Semiconductor

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