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부품번호 FM31L276 기능
기능 64-Kbit/256-Kbit Integrated Processor Companion
제조업체 Cypress Semiconductor
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FM31L276 데이터시트, 핀배열, 회로
FM31L276/FM31L278
64-Kbit/256-Kbit Integrated Processor
Companion with F-RAM
256-Kbit (32 K × 8) Serial (SPI) F-RAM
Features
64-Kbit/256-Kbit ferroelectric random access memory (F-RAM)
Logically organized as 8 K × 8 (FM31L276) / 32 K × 8
(FM31L278)
High-endurance 100 trillion (1014) read/writes
151-year data retention (See the Data Retention and
Endurance table)
NoDelay™ writes
Advanced high-reliability ferroelectric process
High Integration Device Replaces Multiple Parts
Serial nonvolatile memory
Real time clock (RTC)
Low voltage reset
Watchdog timer
Early power-fail warning/NMI
Two 16-bit event counter
Serial number with write-lock for security
Real-time Clock/Calendar
Backup current at 2 V: 1.15 A at +25 C
Seconds through centuries in BCD format
Tracks leap years through 2099
Uses standard 32.768 kHz crystal (6 pF/12.5 pF)
Software calibration
Supports battery or capacitor backup
Processor Companion
Active-low reset output for VDD and watchdog
Programmable low-VDD reset trip point
Manual reset filtered and debounced
Programmable watchdog timer
Dual Battery-backed event counter tracks system intrusions
or other events
Comparator for power-fail interrupt
64-bit programmable serial number with lock
Fast 2-wire serial interface (I2C)
Up to 1-MHz frequency
Supports legacy timings for 100 kHz and 400 kHz
RTC, Supervisor controlled via I2C interface
Device select pins for up to 4 memory devices
Low power consumption
1.5 mA active current at 1 MHz
120 A standby current
Operating voltage: VDD = 2.7 V to 3.6 V
Industrial temperature: –40 C to +85 C
14-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Underwriters laboratory (UL) recognized
Functional Overview
The FM31L276/FM31L278 device integrates F-RAM memory
with the most commonly needed functions for processor-based
systems. Major features include nonvolatile memory, real time
clock, low-VDD reset, watchdog timer, nonvolatile event counter,
lockable 64-bit serial number area, and general purpose
comparator that can be used for a power-fail (NMI) interrupt or
any other purpose.
The FM31L276/FM31L278 is a 64-Kbit/256-Kbit nonvolatile
memory employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is nonvolatile
and performs reads and writes similar to a RAM. This memory is
truly nonvolatile rather than battery backed. It provides reliable
data retention for 151 years while eliminating the complexities,
overhead, and system-level reliability problems caused by other
nonvolatile memories. The FM31L276/FM31L278 is capable of
supporting 1014 read/write cycles, or 100 million times more write
cycles than EEPROM.
The real time clock (RTC) provides time and date information in
BCD format. It can be permanently powered from an external
backup voltage source, either a battery or a capacitor. The
timekeeper uses a common external 32.768 kHz crystal and
provides a calibration mode that allows software adjustment of
timekeeping accuracy.
The processor companion includes commonly needed CPU
support functions. Supervisory functions include a reset output
signal controlled by either a low VDD condition or a watchdog
timeout. RST goes active when VDD drops below a
programmable threshold and remains active for 100 ms after
VDD rises above the trip point. A programmable watchdog timer
runs from 100 ms to 3 seconds. The watchdog timer is optional,
but if enabled it will assert the reset signal for 100 ms if not
restarted by the host before the timeout. A flag-bit indicates the
source of the reset.
A comparator on PFI compares an external input pin to the
onboard 1.2 V reference. This is useful for generating a
power-fail interrupt (NMI) but can be used for any purpose. The
family also includes a programmable 64-bit serial number that
can be locked making it unalterable. Additionally it offers a dual
battery-backed event counter that tracks the number of rising or
falling edges detected on a dedicated input pin.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86392 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 5, 2014




FM31L276 pdf, 반도체, 판매, 대치품
FM31L276/FM31L278
Pinout
Figure 1. 14-pin SOIC pinout
CNT1
1
14 VDD
CNT2
2
13 SCL
A0 3
12 SDA
A1 4
11 X2
CAL/PFO
5
10 X1
RST
6
9 PFI
VSS 7
8 VBAK
Pin Definitions
Pin Name I/O Type
Description
A1-A0
SDA
SCL
Input
Input/Output
Input
Device Select Address 1-0. These pins are used to select one of up to 4 devices of the same type
on the same I2C bus. To select the device, the address value on the three pins must match the
corresponding bits contained in the slave address. The address pins are pulled down internally.
Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended
to be wire-OR'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up
resistor is required.
Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
CNT1, CNT2
Input
Event Counter Inputs. These battery-backed inputs increment counters when an edge is detected
on the corresponding CNT pin. The polarity is programmable. These pins should not be left floating.
Tie to ground if these pins are not used.
X1, X2
Input/Output 32.768 kHz crystal connection. When using an external oscillator, apply the clock to X1 and a DC
mid-level to X2. These pins should be left unconnected if RTC is not used.
RST
Input/Output Reset. This active-low output is open drain with weak pull-up. It is also an input when used as a manual
reset. This pin should be left floating if unused.
PFI Input Early Power-fail Input. Typically connected to an unregulated power supply to detect an early power
failure. This pin must be tied to ground if unused.
CAL/PFO
Output
Calibration/Early Power-fail Output. In calibration mode, this pin supplies a 512 Hz square-wave
output for clock calibration. In normal operation, this is the early power-fail output.
VBAK
Power supply Backup supply voltage. Connected to a 3 V battery or a large value capacitor. If no backup supply
is used, this pin should be tied to ground and the VBC bit should be cleared in the RTC register 0Bh.
The trickle charger is UL recognized and ensures no excessive current when using a lithium battery.
VSS Power supply Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
Document Number: 001-86392 Rev. *B
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FM31L276 전자부품, 판매, 대치품
FM31L276/FM31L278
The comparator is a general purpose device and its application
is not limited to the NMI function.
The comparator is not integrated into the special function
registers except as it shares its output pin with the CAL output.
When the RTC calibration mode is invoked by setting the CAL
bit (register 00h, bit 2), the CAL/PFO output pin will be driven with
a 512 Hz square wave and the comparator will be ignored. Since
most users only invoke the calibration mode during production,
this should have no impact on system operations using the
comparator.
Note The maximum voltage on the comparator input PFI is
limited to 3.75 V under normal operating conditions.
Event Counter
The FM31L276/FM31L278 offers the user two battery-backed
event counters. Input pins CNT1 and CNT2 are programmable
edge detectors. Each clocks a 16-bit counter. When an edge
occurs, the counters will increment their respective registers.
Counter 1 is located in registers 0Dh and 0Eh, Counter 2 is
located in registers 0Fh and 10h. These register values can be
read anytime VDD is above VTP, and they will be incremented as
long as a valid VBAK power source is provided. To read, set the
RC bit register 0Ch bit 3 to 1. This takes a snapshot of all four
counter bytes allowing a stable value even if a count occurs
during the read. The registers can be written by software allowing
the counters to be cleared or initialized by the system. Counts
are blocked during a write operation. The two counters can be
cascaded to create a single 32-bit counter by setting the CC
control bit (register 0Ch, bit 2). When cascaded, the CNT1 input
will cause the counter to increment. CNT2 is not used in this
mode and should be tied to ground.
Figure 6. Event Counter
C NT1
C1P
16-bit Counter
C 2P
CN T2
16-bit Counter
CC
The control bits for event counting are located in register 0Ch.
Counter 1 Polarity is bit C1P, bit 0; Counter 2 Polarity is C2P, bit
1; the Cascade Control is CC, bit 2; and the Read Counter bit is
RC, bit 3.
The polarity bits must be set prior to setting the counter value(s).
If a polarity bit is changed, the counter may inadvertently
increment. If the counter pins are not being used, tie them to
ground.
Serial Number
A memory location to write a 64-bit serial number is provided. It
is a writeable nonvolatile memory block that can be locked by the
user once the serial number is set. The 8 bytes of data and the
lock bit are all accessed via the device ID for the Processor
Companion. Therefore the serial number area is separate and
distinct from the memory array. The serial number registers can
be written an unlimited number of times, so these locations are
general purpose memory. However, once the lock bit is set, the
values cannot be altered and the lock cannot be removed. Once
locked the serial number registers can still be read by the
system.
The serial number is located in registers 11h to 18h. The lock bit
is SNL (register 0Bh, bit 7). Setting the SNL bit to a ‘1’ disables
writes to the serial number registers, and the SNL bit cannot be
cleared.
Real-time Clock Operation
The real-time clock (RTC) is a timekeeping device that can be
battery or capacitor backed for permanently-powered operation.
It offers a software calibration feature that allows high accuracy.
The RTC consists of an oscillator, clock divider, and a register
system for user access. It divides down the 32.768 kHz
time-base and provides a minimum resolution of seconds (1 Hz).
Static registers provide the user with read/write access to the
time values. It includes registers for seconds, minutes, hours,
day-of-the-week, date, months, and years. A block diagram
(Figure 7) illustrates the RTC function.
The user registers are synchronized with the timekeeper core
using R and W bits in register 00h described below. Changing
the R bit from ‘0’ to ‘1’ transfers timekeeping information from the
core into holding registers that can be read by the user. If a
timekeeper update is pending when R is set, then the core will
be updated prior to loading the user registers. The registers are
frozen and will not be updated again until the R bit is cleared to
‘0’. R is used for reading the time.
Setting the W bit to ‘1’ locks the user registers. Clearing it to ‘0’
causes the values in the user registers to be loaded into the
timekeeper core. W bit is used for writing new time values. Users
should be certain not to load invalid values, such as FFh, to the
timekeeping registers. Updates to the timekeeping core occur
continuously except when locked.
Document Number: 001-86392 Rev. *B
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