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CY7C1463KV33 데이터시트 PDF




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부품번호 CY7C1463KV33 기능
기능 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM
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CY7C1463KV33 데이터시트, 핀배열, 회로
CY7C1461KV33
CY7C1463KV33
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V and 2.5 V I/O power supply
Fast clock-to-output times
6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self timed writes
Asynchronous Output Enable
CY7C1461KV33,
CY7C1463KV33
available
JEDEC-standard Pb-free 100-pin TQFP packages
in
Three chip enables for simple depth expansion
Automatic power down feature available using ZZ mode or CE
deselect
Burst capability – linear or interleaved burst order
Low standby power
Functional Description
The CY7C1461KV33/CY7C1463KV33 are 3.3 V,
1M × 36/2M × 18 Synchronous Flow-Through Burst SRAMs
designed specifically to support unlimited true back-to-back read
and write operations without the insertion of wait states. The
CY7C1461KV33/CY7C1463KV33 is equipped with the advanced
NoBL logic required to enable consecutive read and write
operations with data being transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent write-read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
133 MHz Unit
6.5 ns
× 18 150 mA
× 36 170
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66681 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 7, 2016




CY7C1463KV33 pdf, 반도체, 판매, 대치품
CY7C1461KV33
CY7C1463KV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Partial Truth Table for Read/Write ................................ 11
Partial Truth Table for Read/Write ................................ 11
Maximum Ratings ........................................................... 12
Operating Range ............................................................. 12
Neutron Soft Error Immunity ......................................... 12
Electrical Characteristics ............................................... 12
Capacitance .................................................................... 14
Thermal Resistance ........................................................ 14
AC Test Loads and Waveforms ..................................... 14
Switching Characteristics .............................................. 15
Switching Waveforms .................................................... 16
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC®Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 001-66681 Rev. *G
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CY7C1463KV33 전자부품, 판매, 대치품
CY7C1461KV33
CY7C1463KV33
Pin Definitions
Pin Name
I/O
Description
A0, A1, A
BWA, BWB,
BWC, BWD
WE
Input-Synchronous
Input-Synchronous
Input-Synchronous
Address Inputs. Used to select one of the address locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-Synchronous Advance or Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After deselecting, drive ADV/LD LOW
to load a new address.
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
CE2
CE3
OE
Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select or deselect the device.
Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select or deselect the device.
Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select or deselect the device.
Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected.
CEN
Input-Synchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not
deselect the device, use CEN to extend the previous cycle when required.
ZZ Input-Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non time critical sleep condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs
I/O-Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D]
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPX
MODE
VDD
VDDQ
VSS
NC
I/O-Synchronous
Input Strap Pin
Power Supply
I/O Power Supply
Ground
N/A
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
sequences, DQPX is controlled by BWX correspondingly.
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
Power Supply Inputs to the Core of the Device.
Power Supply for I/O Circuitry.
Ground for the Device.
No Connects. Not internally connected to the die.
NC/72M
N/A Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A Not Connected to the Die. Can be tied to any voltage level.
Document Number: 001-66681 Rev. *G
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CY7C1463KV33

36-Mbit (1M x 36/2M x 18) Flow-Through SRAM

Cypress Semiconductor
Cypress Semiconductor

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