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CY7C1471BV25 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 CY7C1471BV25은 전자 산업 및 응용 분야에서
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부품번호 CY7C1471BV25 기능
기능 72-Mbit (2 M x 36) Flow-Through SRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CY7C1471BV25 데이터시트, 핀배열, 회로
CY7C1471BV25
72-Mbit (2 M × 36)
Flow-Through SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data transfers on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte Write capability
2.5-V I/O supply (VDDQ)
Fast clock-to-output times
6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self timed writes
Asynchronous Output Enable (OE)
CY7C1471BV25 available in JEDEC-standard Pb-free 100-pin
TQFP package.
Three Chip Enables (CE1, CE2, CE3) for simple depth
expansion.
Automatic power down feature available using ZZ mode or CE
deselect.
Burst Capability – linear or interleaved burst order
Low standby power
Functional Description
The CY7C1471BV25, is 2.5 V, 2 M × 36 synchronous flow
through burst SRAMs designed specifically to support unlimited
true back-to-back read or write operations without the insertion
of wait states. The CY7C1471BV25, is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive read or write operations with data transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz
6.5
305
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15013 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 11, 2016




CY7C1471BV25 pdf, 반도체, 판매, 대치품
CY7C1471BV25
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) Pinout
BYTE C
BYTE D
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1471BV25
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSS
75
74
DQB
DQB
BYTE B
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57
DQA
BYTE A
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 DQPA
Document Number: 001-15013 Rev. *N
Page 4 of 22

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CY7C1471BV25 전자부품, 판매, 대치품
CY7C1471BV25
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00 01 10
01 00 11
10 11 00
11 10 01
Fourth
Address
A1:A0
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
00
01
Second
Address
A1:A0
01
10
Third
Address
A1:A0
10
11
10 11 00
11 00 01
Fourth
Address
A1:A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Test Conditions
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
ZZ active to sleep current
This parameter is sampled
ZZ Inactive to exit sleep current This parameter is sampled
Min
2tCYC
0
Max
120
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Document Number: 001-15013 Rev. *N
Page 7 of 22

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CY7C1471BV25

72-Mbit (2 M x 36) Flow-Through SRAM

Cypress Semiconductor
Cypress Semiconductor

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