PDF CY7C1460KV25 Data sheet ( Hoja de datos )

Número de pieza	CY7C1460KV25
Descripción	36-Mbit (1M x 36/2M x 18) Pipelined SRAM
Fabricantes	Cypress Semiconductor
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CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades are 250 MHz, 200 MHz, and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte Write capability ■ 2.5-V core power supply ■ 2.5-V I/O power supply ■ Fast clock-to-output times ❐ 2.5 ns (for 250-MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and CY7C1462KVE25 available in JEDEC-standard Pb-free 100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA packages. ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ Burst capability — linear or interleaved burst order ■ “ZZ” sleep mode option ■ On-chip error correction code (ECC) to reduce soft error rate (SER) Selection Guide Maximum access time Maximum operating current Description Functional Description The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/ CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/ CY7C1462KVE25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1460KV25/CY7C1462KV25/ CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the byte write selects BWa–BWd for CY7C1460KV25/CY7C1460KVE25 and BWa–BWb for CY7C1462KV25/CY7C1462KVE25 and a write enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. 250 MHz 200 MHz 167 MHz Unit 2.5 3.2 3.4 ns × 18 220 190 170 mA × 36 240 210 190 Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-66679 Rev. I • San Jose, CA 95134-1709 • 408-943-2600 Revised July 5, 2016 1 page CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 Contents Pin Configurations ........................................................... 6 Pin Definitions .................................................................. 8 Functional Overview ........................................................ 9 Single Read Accesses ................................................ 9 Burst Read Accesses .................................................. 9 Single Write Accesses ............................................... 10 Burst Write Accesses ................................................ 10 Sleep Mode ............................................................... 10 On-Chip ECC ............................................................ 10 Interleaved Burst Address Table ............................... 11 Linear Burst Address Table ....................................... 11 ZZ Mode Electrical Characteristics ............................ 11 Truth Table ...................................................................... 12 Partial Write Cycle Description ..................................... 13 Partial Write Cycle Description ..................................... 13 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14 Disabling the JTAG Feature ...................................... 14 Test Access Port (TAP) ............................................. 14 PERFORMING A TAP RESET .................................. 14 TAP REGISTERS ...................................................... 14 TAP Instruction Set ................................................... 15 TAP Controller State Diagram ....................................... 16 TAP Controller Block Diagram ...................................... 16 TAP Timing ...................................................................... 16 TAP AC Switching Characteristics ............................... 17 2.5 V TAP AC Test Conditions ....................................... 18 2.5 V TAP AC Output Load Equivalent ......................... 18 TAP DC Electrical Characteristics and Operating Conditions ............................................. 18 Identification Register Definitions ................................ 19 Scan Register Sizes ....................................................... 19 Identification Codes ....................................................... 19 Boundary Scan Order .................................................... 20 Maximum Ratings ........................................................... 21 Operating Range ............................................................. 21 Neutron Soft Error Immunity ......................................... 21 Electrical Characteristics ............................................... 21 Capacitance .................................................................... 23 Thermal Resistance ........................................................ 23 AC Test Loads and Waveforms ..................................... 23 Switching Characteristics .............................................. 24 Switching Waveforms .................................................... 25 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Document History Page ................................................. 31 Sales, Solutions, and Legal Information ...................... 32 Worldwide Sales and Design Support ....................... 32 Products .................................................................... 32 PSoC® Solutions ...................................................... 32 Cypress Developer Community ................................. 32 Technical Support ..................................................... 32 Document Number: 001-66679 Rev. I Page 5 of 32 5 Page CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 00 01 10 01 00 11 10 11 00 11 10 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ  VDD 0.2 V ZZVDD  0.2 V ZZ  0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 75 2tCYC – 2tCYC – Unit mA ns ns ns ns Document Number: 001-66679 Rev. *I Page 11 of 32 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C1460KV25	36-Mbit (1M x 36/2M x 18) Pipelined SRAM	Cypress Semiconductor

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