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부품번호 CY7C1460KVE33 기능
기능 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
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CY7C1460KVE33 데이터시트, 핀배열, 회로
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
36-Mbit (1M × 36/2M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Pin-compatible and functionally equivalent to Zero Bus
Turnaround (ZBT™)
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully-registered (inputs and outputs) for pipelined operation
Byte write capability
3.3-V power supply
3.3-V/2.5-V I/O power supply
Fast clock-to-output time
2.5 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33
available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 165-ball FBGA packages
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability—linear or interleaved burst order
“ZZ” sleep mode option
On-chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Functional Description
The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are
3.3 V, 1M × 36, and 2M × 18 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. 6
This feature dramatically improves the throughput of data in
systems that require frequent write and read transitions. The
CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices
are pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1460KV33/CY7C1460KVE33 and
BWa–BWb for CY7C1462KVE33) and a write enable (WE) input.
All writes are conducted with on-chip synchronous self-timed
write circuitry.
Three synchronous chip enables (CE1, CE2, and CE3) and an
asynchronous output enable (OE) enable easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
250 MHz 200 MHz 167 MHz Unit
2.5 3.2 3.4 ns
× 18 220 190 170 mA
× 36 240 210 190
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66680 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 5, 2016




CY7C1460KVE33 pdf, 반도체, 판매, 대치품
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 9
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
On-Chip ECC .............................................................. 9
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Write Cycle Description ..................................... 12
Partial Write Cycle Description ..................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 15
TAP Timing Diagram ...................................................... 15
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-66680 Rev. *K
Page 4 of 31

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CY7C1460KVE33 전자부품, 판매, 대치품
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-synchronous Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK.
BWa, BWb,
BWc, BWd
WE
Input-synchronous
Input-synchronous
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and
DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-synchronous Advance/load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW to load a new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1 Input-synchronous Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device.
CE2 Input-synchronous Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE3 Input-synchronous Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
OE Input-asynchronous Output enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
CEN
Input-synchronous Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa, DQb, DQc,
DQd
I/O-synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the
data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQPa,DQPb,
DQPc,DQPd
MODE
I/O-synchronous
Input strap pin
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled
by BWc, and DQPd is controlled by BWd.
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE defaults HIGH, to an interleaved burst order.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
synchronous
TDI JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
synchronous
TMS
Test mode select This pin controls the test access port state machine. Sampled on the rising edge of TCK.
synchronous
TCK
JTAG-clock Clock input to the JTAG circuitry.
Document Number: 001-66680 Rev. *K
Page 7 of 31

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부품번호상세설명 및 기능제조사
CY7C1460KVE33

36-Mbit (1M x 36/2M x 18) Pipelined SRAM

Cypress Semiconductor
Cypress Semiconductor

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