CY7C09349AV Datasheet PDF - Cypress Semiconductor
| Part Number | CY7C09349AV | |
| Description | 3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM | |
| Manufacturers | Cypress Semiconductor | |
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CY7C09359AV3.3 V 4 K/8 K × 18
Synchronous Dual Port Static RAM
CY7C09349AV
CY7C09359AV
3.3 V 4 K/8 K × 18
Synchronous Dual Port Static RAM
3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM
Features
■ True dual ported memory cells which allow simultaneous
access of the same memory location
■ Two flow-through/pipelined devices
❐ 4 K × 18 organization (CY7C09349AV)
❐ 8 K × 18 organization (CY7C09359AV)
■ Three modes
❐ Flow-through
❐ Pipelined
❐ Burst
■ Pipelined output mode on both ports allows fast 67-MHz
operation
■ 0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
Logic Block Diagram
R/WL
UBL
■ High-speed clock to data access 9 and 12 ns (max)
■ 3.3 V low operating power
❐ Active = 135 mA (typical)
❐ Standby = 10 µA (typical)
■ Fully synchronous interface for easier operation
■ Burst counters increment addresses internally
❐ Shorten cycle times
❐ Minimize bus noise
❐ Supported in flow-through and pipelined modes
■ Dual chip enables for easy depth expansion
■ Upper and lower byte controls for bus matching
■ Automatic power-down
■ Available in 100-pin thin quad flat pack (TQFP)
For a complete list of related documentation, click here.
R/WR
UBR
CE0L
CE1L
LBL
OEL
1
0
0/1
1 CE0R
0 CE1R
0/1 LBR
OER
FT/PipeL
I/O9L–I/O17L
I/O0L–I/O8L
[1]
A0L–A11/12L
CLKL
ADSL
CNTENL
CNTRSTL
1b 0b 1a 0a
0/1 b
a
9
9
12/13
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual Ported
RAM Array
0a 1a 0b 1b
a b 0/1
9
FT/PipeR
I/O9R–I/O17R
Counter/
Address
Register
Decode
9
12/13
I/O0R–I/O8R
[1]
A0R–A11/12R
CLKR
ADSR
CNTENR
CNTRSTR
Note
1. A0–A11 for 4 K; A0–A12 for 8 K devices.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-63888 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 26, 2014
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CY7C09349AV
CY7C09359AV
Pin Definitions
Left Port
A0L–A12L
ADSL
CE0L, CE1L
CLKL
CNTENL
CNTRSTL
I/O0L–I/O17L
LBL
UBL
OEL
R/WL
FT/PIPEL
GND
NC
VCC
Right Port
A0R–A12R
ADSR
CE0R, CE1R
CLKR
CNTENR
CNTRSTR
I/O0R–I/O17R
LBR
UBR
OER
R/WR
FT/PIPER
Description
Address inputs (A0–A11 for 4 K, A0–A12 for 8 K devices).
Address strobe input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
Chip enable input. To select either the left or right port, both CE0 and CE1 must be asserted to their
active states (CE0 VIL and CE1 VIH).
Clock signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
Counter enable input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter reset input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data bus input/output (I/O0–I/O15 for ×16 devices).
Lower byte select input. Asserting this signal LOW enables read and write operations to the lower
byte (I/O0–I/O8 for ×18, I/O0–I/O7 for ×16) of the memory array. For read operations both the LB
and OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper byte select input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
Output enable input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/write enable input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow-through/pipelined select input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground input.
No connect.
Power input.
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage temperature................................ –65 C to +150 C
Ambient temperature with power applied . –55 C to +125 C
Supply voltage to ground potential ...............–0.5 V to +4.6 V
DC voltage applied to
outputs in high Z state ......................... –0.5 V to VCC + 0.5 V
DC input voltage .................................. –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... > 2001 V
Latch-up current ..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0 C to +70 C
–40 C to +85 C
VCC
3.3 V ± 300 mV
3.3 V ± 300 mV
Document Number: 001-63888 Rev. *C
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