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PDF CYD02S36V Data sheet ( Hoja de datos )
| Número de pieza | CYD02S36V | |
| Descripción | 3.3 V (64 K x 36) Synchronous Dual-Port RAM | |
| Fabricantes | Cypress Semiconductor | |
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CYD02S36V/36VA
FLEx36™ 3.3 V (64 K × 36) Synchronous
Dual-Port RAM
FLEx36™ 3.3 V (64 K × 36) Synchronous Dual-Port RAM
Features
■ True dual-ported memory cells that enable simultaneous
access of the same memory location
■ Synchronous pipelined operation
■ Pipelined output mode allows fast operation
■ 0.18 micron complementary metal oxide semiconductor
(CMOS) for optimum speed and power
■ High speed clock to data access
■ 3.3 V low power
❐ Active as low as 225 mA (typ.)
❐ Standby as low as 55 mA (typ.)
■ Mailbox function for message passing
■ Global master reset
■ Separate byte enables on both ports
■ Commercial and industrial temperature ranges
■ IEEE 1149.1-compatible joint test action group (JTAG)
boundary scan
■ 256 Ball fine-pitch ball grid array (FBGA) (1-mm pitch)
■ Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
■ Counter readback on address lines
■ Mask register readback on address lines
■ Dual chip enables on both ports for easy depth expansion
■ Seamless migration to next-generation dual-port family
Product Selection Guide
Density
Part number
Max. speed (MHz)
Max. access time – clock to data (ns)
Typical operating current (mA)
Package
Functional Description
The FLEx36™ family includes 2-Mbit pipelined, synchronous,
true dual-port static RAMs that are high speed, low power 3.3 V
CMOS. Two ports are provided, permitting independent,
simultaneous access to any location in memory. A particular port
can write to a certain location while another port is reading that
location. The result of writing to the same location by more than
one port at the same time is undefined. Registers on control,
address, and data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
For a complete list of related documentation, click here.
2-Mbit
(64 K × 36)
CYD02S36V/36VA
167
4.4
225
256 FBGA
(17 mm x 17 mm)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06076 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 27, 2014
1 page  
CYD02S36V/36VA
Pin Definitions
Left Port
Right Port
Description
A0L–A15L
BE0L–BE3L
BUSYL[5,8]
CL
CE0L
CE1L
DQ0L–DQ35L
OEL
A0R–A15R
BE0R–BE3R
BUSYR[5,8]
CR
CE0R
CE1R
DQ0R–DQ35R
OER
Address inputs
Byte enable inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
Port busy output. When the collision is detected, a BUSY is asserted.
Input clock signal
Active low chip enable input
Active high chip enable input
Data bus input/output.
Output enable input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during read operations.
INTL
INTR
Mailbox interrupt flag output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW
when the right port writes to the mailbox location of the left port, and vice versa. An interrupt
to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL[5,7]
LowSPDR[5,7] Port low speed select input.
PORTSTD[1:0]L[5,7] PORTSTD[1:0]R[5,7] Port address/control/data io standard select inputs.
R/WL
R/WR
Read/write enable input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
READYL[5,8]
READYR[5,8] Port ready output. This signal is asserted when a port is ready for normal operation.
CNT/MSKL
CNT/MSKR
Port counter/mask select input. Counter control input.
ADSL
ADSR
Port counter address load strobe input. Counter control input.
CNTENL
CNTENR
Port counter enable input. Counter control input.
CNTRSTL
CNTRSTR
Port counter reset input. Counter control input.
CNTINTL
CNTINTR
Port counter interrupt output. This pin is asserted LOW when the unmasked portion of
the counter is incremented to all “1s”.
WRPL[5,6]
RETL[5,6]
FTSELL[5,6]
WRPR[5,6]
RETR[5,6]
FTSELR[5,6]
Port counter wrap input. The burst counter wrap control input.
Port counter retransmit input. Counter control input.
Flow-through select. Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
VREFL[5,7]
VREFR[5,7]
Port external high-speed io reference input.
VDDIOL
REVL [5, 6, 7]
VDDIOR
REVR[5, 6, 7]
Port I/O power supply.
Reserved pins for future features.
MRST
Master reset input. MRST is an asynchronous input signal and affects both ports. A maser
reset operation is required at power up.
TRST[5,8]
JTAG reset input.
TMS
JTAG test mode select input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI JTAG test data input. Data on the TDI input is shifted serially into selected registers.
TCK
JTAG test clock input.
TDO
JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS Ground inputs.
Notes
5. This ball represents a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
6. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
7. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
8. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
Document Number: 38-06076 Rev. *M
Page 5 of 29
5 Page 
CYD02S36V/36VA
Table 4. Scan Register Sizes
Register Name
Instruction
Bypass
Identification
Boundary Scan
Bit Size
4
1
32
n[19]
Table 5. Instruction Identification Codes
Instruction
EXTEST
BYPASS
IDCODE
HIGHZ
CLAMP
SAMPLE/PRELOAD
NBSRST
RESERVED
Code
0000
1111
1011
0111
0100
1000
1100
All other codes
Description
Captures the input/output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
Other combinations are reserved. Do not use other than the above.
Note
19. See details in the device BSDL files.
Document Number: 38-06076 Rev. *M
Page 11 of 29
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