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부품번호 CY7C4122KV13 기능
기능 144-Mbit QDR-IV XP SRAM
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CY7C4122KV13 데이터시트, 핀배열, 회로
CY7C4122KV13/CY7C4142KV13
144-Mbit QDR™-IV XP SRAM
144-Mbit QDR™-IV XP SRAM
Features
Configurations
144-Mbit density (8M × 18, 4M × 36)
Total Random Transaction Rate[1] of 2132 MT/s
Maximum operating frequency of 1066 MHz
Read latency of 8.0 clock cycles and write latency of 5.0 clock
cycles
Eight-bank architecture enables one access per bank per cycle
Two-word burst on all accesses
Dual independent bidirectional data ports
Double data rate (DDR) data ports
Supports concurrent read/write transactions on both ports
Single address port used to control both data ports
DDR address signaling
Single data rate (SDR) control signaling
High-speed transceiver logic (HSTL) and stub series termi-
nated logic (SSTL) compatible signaling (JESD8-16A
compliant)
I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV
Pseudo open drain (POD) signaling (JESD8-24 compliant)
I/O VDDQ = 1.1 V ± 50 mV or 1.2 V ± 50 mV
Core voltage
VDD = 1.3 V ± 40 mV
On-die termination (ODT)
Programmable for clock, address/command, and data inputs
Internal self-calibration of output impedance through ZQ pin
Bus inversion to reduce switching noise and power
Programmable on/off for address and data
Address bus parity error protection
Training sequence for per-bit deskew
On-chip error correction code (ECC) to reduce soft error rate
(SER)
JTAG 1149.1 test access port (JESD8-26 compliant)
1.3-V LVCMOS signaling
Available in 361-ball FCBGA Pb-free package (21 × 21 mm)
CY7C4122KV13 – 8M × 18
CY7C4142KV13 – 4M × 36
Functional Description
The QDR™-IV XP (Xtreme Performance) SRAM is a
high-performance memory device optimized to maximize the
number of random transactions per second by the use of two
independent bidirectional data ports.
These ports are equipped with DDR interfaces and designated
as port A and port B respectively. Accesses to these two data
ports are concurrent and independent of each other. Access to
each port is through a common address bus running at DDR. The
control signals are running at SDR and determine if a read or
write should be performed.
There are three types of differential clocks:
(CK, CK#) for address and command clocking
(DKA, DKA#, DKB, DKB#) for data input clocking
(QKA, QKA#, QKB, QKB#) for data output clocking
Addresses for port A are latched on the rising edge of the input
clock (CK), and addresses for port B are latched on the falling
edge of the input clock (CK).
This QDR-IV XP SRAM is internally partitioned into eight internal
banks. Each bank can be accessed once for every clock cycle,
enabling the SRAM to operate at high frequencies.
The QDR-IV XP SRAM device is offered in a two-word burst
option and is available in × 18 and × 36 bus width configurations.
For an ×18 bus-width configuration, there are 22 address bits,
and for an ×36 bus width configuration, there are 21 address bits
respectively.
An on-chip ECC circuitry detects and corrects all single-bit
memory errors including those induced by soft error events, such
as cosmic rays and alpha particles. The resulting SER of these
devices is expected to be less than 0.01 FITs/Mb, a
four-order-of-magnitude improvement over previous generation
SRAMs.
For a complete list of related resources, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
QDR-IV
2132 (MT/s)
QDR-IV
1866 (MT/s)
Unit
1066
933 MHz
×18 4100
3400
mA
×36 4500
4000
Note
1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured
in million transactions per second.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-68255 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 29, 2016




CY7C4122KV13 pdf, 반도체, 판매, 대치품
CY7C4122KV13/CY7C4142KV13
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Clocking ....................................................................... 9
Command Cycles ........................................................ 9
Read and Write Data Cycles ....................................... 9
Banking Operation ....................................................... 9
Address and Data Bus Inversion ................................. 9
Address Parity ........................................................... 10
Port Enable ................................................................ 10
On-Die Termination (ODT) Operation ....................... 10
JTAG Operation ........................................................ 10
Power-Up and Reset ................................................. 10
Operation Modes ....................................................... 11
Deskew Training Sequence ...................................... 12
I/O Signaling Standards ............................................ 12
Initialization ................................................................ 13
Configuration Registers ............................................. 14
Configuration Registers Description .......................... 15
Configuration Register Definitions ............................. 15
I/OType and Port Enable Bit Definitions .................... 17
ODT Termination Bit Definitions ................................ 18
Drive Strength Bit Definitions .................................... 19
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 20
Test Access Port ....................................................... 20
TAP Registers ........................................................... 20
TAP Instruction Set ................................................... 20
TAP Controller State Diagram ....................................... 22
TAP Controller Block Diagram ...................................... 23
TAP Electrical Characteristics ...................................... 24
TAP AC Switching Characteristics ............................... 24
TAP Timing Diagram ...................................................... 25
Identification Register Definitions ................................ 26
Scan Register Sizes ....................................................... 26
Instruction Codes ........................................................... 26
Boundary Scan Order .................................................... 27
Maximum Ratings ........................................................... 30
Operating Range ............................................................. 30
Neutron Soft Error Immunity ......................................... 30
Electrical Characteristics ............................................... 30
Capacitance .................................................................... 32
Thermal Resistance ........................................................ 32
AC Test Load and Waveform ......................................... 32
Switching Characteristics .............................................. 33
Switching Waveforms .................................................... 35
Ordering Information ...................................................... 42
Ordering Code Definitions ......................................... 42
Package Diagram ............................................................ 43
Acronyms ........................................................................ 44
Document Conventions ................................................. 44
Units of Measure ....................................................... 44
Document History Page ................................................. 45
Sales, Solutions, and Legal Information ...................... 46
Worldwide Sales and Design Support ....................... 46
Products .................................................................... 46
PSoC® Solutions ...................................................... 46
Cypress Developer Community ................................. 46
Technical Support ..................................................... 46
Document Number: 001-68255 Rev. *P
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CY7C4122KV13 전자부품, 판매, 대치품
CY7C4122KV13/CY7C4142KV13
Pin Definitions
Pin Name
I/Os
Pin Description
CK, CK#
Input Clock
Address/Command Input Clock. CK and CK# are differential clock inputs. All control and address
input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples
the control and address inputs for port A, while the falling edge of CK samples the control and address
inputs for port B. CK# is 180 degrees out of phase with CK.
A[x:0]
Input
Address Inputs. Sampled on the rising edge of both CK and CK# clocks during active read and write
operations. These address inputs are used for read and write operations on both ports. The lower
three address pins (A0, A1, and A2) select the bank that will be accessed. These address inputs are
also known as bank address pins.
For (×36) data width - Address inputs A[20:0] are used and A[24:21] are reserved.
For (×18) data width - Address inputs A[21:0] are used and A[24:22] are reserved.
The reserved address inputs are No Connects and may be tied high, tied low, or left floating.
AP
Input
Address Parity Input. Used to provide even parity across the address pins.
For (×36) data width - AP covers address inputs A[20:0]
For (×18) data width - AP covers address inputs A[21:0]
PE# Output Address Parity Error Flag. Asserted LOW when address parity error is detected. Once asserted,
PE# will remain LOW until cleared by a Configuration Register command.
AINV
Input
Address Inversion Pin for Address and Address Parity Inputs.
For (×36) data width - AINV covers address inputs A[20:0] and the address parity input (AP).
For (×18) data width - AINV covers address inputs A[21:0] and the address parity input (AP).
DKA[1:0],
DKA#[1:0],
DKB[1:0],
DKB#[1:0]
Input
Data Input Clock.
DKA[0] / DKA#[0] controls the DQA[17:0] inputs for ×36 configuration and DQA[8:0] inputs for ×18
configuration respectively
DKA[1] / DKA#[1] controls the DQA[35:18] inputs for ×36 configuration and DQA[17:9] inputs for ×18
configuration respectively
DKB[0] / DKB#[0] controls the DQB[17:0] inputs for ×36 configuration and DQB[8:0] inputs for ×18
configuration respectively
DKB[1] / DKB#[1] controls the DQB[35:18] inputs for ×36 configuration and DQB[17:9] inputs for ×18
configuration respectively
QKA[1:0],
QKA#[1:0],
QKB[1:0],
QKB#[1:0]
Output
Data Output Clock.
QKA[0] / QKA#[0] controls the DQA[17:0] outputs for × 36 configuration and DQA[8:0] outputs for ×18
configuration respectively
QKA[1] / QKA#[1] controls the DQA[35:18] outputs for × 36 configuration and DQA[17:9] outputs for
×18 configuration respectively
QKB[0] / QKB#[0] controls the DQB[17:0] outputs for × 36 configuration and DQB[8:0] outputs for ×18
configuration respectively
QKB[1] / QKB#[1] controls the DQB[35:18] outputs for × 36 configuration and DQB[17:9] outputs for
×18 configuration respectively
DQA[x:0],
DQB[x:0]
DINVA[1:0],
DINVB[1:0]
Input/Output
Input/Output
Data Input/Output.Bidirectional data bus.
For (×36) data width DQA[35:0]; DQB[35:0]
For (×18) data width DQA[17:0]; DQB[17:0]
Data Inversion Pin for DQ Data Bus.
DINVA[0] covers DQA[17:0] for ×36 configuration and DQA[8:0] for ×18 configuration respectively
DINVA[1] covers DQA[35:18] for ×36 configuration and DQA[17:9] for ×18 configuration respectively
DINVB[0] covers DQB[17:0] for ×36 configuration and DQB[8:0] for ×18 configuration respectively
DINVB[1] covers DQB[35:18] for ×36 configuration and DQB[17:9] for ×18 configuration respectively
LDA#, LDB#
Input
Synchronous Load Input. LDA# is sampled on the rising edge of the CK clock, while LDB# is
sampled on the falling edge of CK clock. LDA# enables commands for data port A and LDB# enables
commands for data port B. LDx# enables the commands when LDx# is LOW and disables the
commands when LDx# is HIGH. When the command is disabled, new commands are ignored, but
internal operations continue.
Document Number: 001-68255 Rev. *P
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CY7C4122KV13

144-Mbit QDR-IV XP SRAM

Cypress Semiconductor
Cypress Semiconductor

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