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PDF CY7C1352G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1352G | |
| Descripción | 4-Mbit (256K x 18) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1352G
4-Mbit (256K × 18) Pipelined SRAM
with NoBL™ Architecture
4-Mbit (256K × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Byte write capability
■ 256K × 18 common I/O architecture
■ 3.3 V core power supply (VDD)
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 4.0 ns (for 133-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable (OE)
■ Available in Pb-free 100-pin TQFP package
■ Burst capability – linear or interleaved burst order
■ ZZ sleep mode option and stop clock option
Functional Description
The CY7C1352G is a 3.3 V, 256K × 18 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1352G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 4.0 ns
(133-MHz device).
Write operations are controlled by the two byte write select
(BW[A:B]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz
4.0
225
40
Unit
ns
mA
mA
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05514 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 3, 2016
1 page  
CY7C1352G
Pin Definitions
Name
A0, A1, A
BW[A:B]
WE
ADV/LD
CLK
CE1
CE2
CE3
OE
CEN
ZZ[2]
DQs
I/O Description
Input- Address inputs used to select one of the 256 K address location. Sampled at the rising edge of the
synchronous CLK. A[1:0] are fed to the two-bit burst counter.
Input- Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
Input- Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input- Advance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input- Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
Input- Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
Input- Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the DQ pins are allowed to behave as
outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input- Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Input- ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an
internal pull-down.
I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and
DQP[A:B] are placed in a tri-state condition. The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19.
Document Number: 38-05514 Rev. *O
Page 5 of 22
5 Page 
CY7C1352G
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature 65 °C to +150 °C
Ambient temperature with
power applied 55 °C to +125 °C
Supply voltage on VDD relative to GND 0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND 0.5 V to +VDD
DC voltage applied to outputs
in tri-state 0.5 V to VDDQ + 0.5 V
DC input voltage 0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Ambient
Range Temperature (TA)
Commercial 0 °C to +70 °C
VDD
3.3 V – 5% /
+10%
VDDQ
2.5 V – 5%
to VDD
Electrical Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Test Conditions
VDD
VDDQ
VOH
VOL
VIH
VIL
Power supply voltage
I/O supply voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [12]
Input LOW voltage [12]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
for 2.5 V I/O
for 3.3 V I/O
for 2.5 V I/O
IX Input leakage current except ZZ GND VI VDDQ
and MODE
Input current of MODE
Input = VSS
Input = VDD
Input current of ZZ
Input = VSS
Input = VDD
IOZ
Output leakage current
GND VI VDDQ, output disabled
IDD
VDD operating supply current VDD = Max, IOUT = 0 mA,
7.5-ns cycle,
f = fMAX = 1/tCYC
133 MHz
ISB1
Automatic CE power-down
VDD = Max, device deselected, 7.5-ns cycle,
current – TTL inputs
VIN VIH or VIN VIL,
133 MHz
f = fMAX = 1/tCYC
ISB2
Automatic CE power-down
VDD = Max, device deselected, 7.5-ns cycle,
current – CMOS inputs
VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f=0
ISB3
Automatic CE power-down
VDD = Max, device deselected, 7.5-ns cycle,
current – CMOS Inputs
VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f = fMAX = 1/tCYC
Notes
12. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
13. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Min
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
5
30
–
–5
–
–5
–
–
–
–
Max Unit
3.6 V
VDD
V
–V
–V
0.4 V
0.4 V
VDD + 0.3 V
VDD + 0.3 V
0.8
V
V
V
0.7 V
5 µA
– µA
5 µA
– µA
30 µA
5 µA
225 mA
90 mA
40 mA
75 mA
Document Number: 38-05514 Rev. *O
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY7C1352G.PDF ] | |
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