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PDF CY7C1354C Data sheet ( Hoja de datos )
| Número de pieza | CY7C1354C | |
| Descripción | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1354C
CY7C1356C
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin-compatible and functionally equivalent to ZBT
■ Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 166 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 3.3 V power supply (VDD)
■ 3.3 V or 2.5 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 2.8 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in Pb-free 100-pin TQFP package, Pb-free, and non
Pb-free 119-ball BGA package and 165-ball FBGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1354C/CY7C1356C[1] are 3.3 V,
256K × 36/512K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The CY7C1354C/CY7C1356C
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature greatly improves the throughput
of data in systems that require frequent write/read transitions.
The CY7C1354C/CY7C1356C are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354C and BWa–BWb for CY7C1356C)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.8
250
40
200 MHz
3.2
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05538 Rev. *S
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2016
1 page  
CY7C1354C
CY7C1356C
Pin Configurations (continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout
CY7C1354C (256K × 36)
1 234
A VDDQ
A
A NC/18M
B NC/576M
C NC/1G
CE2
A
D DQc DQPc
E DQc
F VDDQ
G DQc
H DQc
J VDDQ
K DQd
L DQd
DQc
DQc
DQc
DQc
VDD
DQd
DQd
M VDDQ DQd
N DQd DQd
P
DQd
DQPd
A
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
ADV/LD
VDD
NC
CE1
OE
A
WE
VDD
CLK
NC
CEN
A1
A0
R NC/144M
A
MODE
T
NC NC/72M
A
VDD
A
U VDDQ TMS TDI TCK
5
A
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
TDO
CY7C1356C (512K × 18)
6
A
CE3
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
NC/36M
NC
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC/288M
ZZ
VDDQ
12
A VDDQ
A
B NC/576M CE2
C NC/1G
A
D DQb
NC
E NC DQb
F VDDQ NC
G NC DQb
H DQb
NC
J VDDQ VDD
K NC DQb
L DQb NC
M VDDQ DQb
N DQb
NC
P NC DQPb
R NC/144M
A
T NC/72M
A
U VDDQ TMS
3
A
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
TDI
4
NC/18M
ADV/LD
VDD
NC
CE1
OE
A
WE
VDD
CLK
NC
CEN
A1
A0
VDD
NC/36M
TCK
5
A
A
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
TDO
6
A
CE3
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC/288M
ZZ
VDDQ
Document Number: 38-05538 Rev. *S
Page 5 of 36
5 Page 
CY7C1354C
CY7C1356C
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1354C follows. [9, 10, 11, 12]
Function (CY7C1354C)
Read
Write– no bytes written
Write byte a –(DQa and DQPa)
Write byte b – (DQb and DQPb)
Write bytes b, a
Write byte c –(DQc and DQPc)
Write bytes c, a
Write bytes c, b
Write bytes c, b, a
WE
H
L
L
L
L
L
L
L
L
Write byte d –(DQd and DQPd)
Write bytes d, a
L
L
Write bytes d, b
Write bytes d, b, a
Write bytes d, c
Write bytes d, c, a
Write bytes d, c, b
Write all bytes
L
L
L
L
L
L
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1356C follows. [9, 10, 11, 12]
Read
Function (CY7C1356C)
WE
H
Write – no bytes written
L
Write byte a (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write both bytes
L
L
L
BWd
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BWc
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
BWb
x
H
H
L
L
BWb
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
BWa
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
BWa
x
H
L
H
L
Notes
9. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
10. Write is defined by WE and BWX. See Write Cycle Description table for details.
11. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05538 Rev. *S
Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1354C.PDF ] | |
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