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PDF CY7C1354D Data sheet ( Hoja de datos )
| Número de pieza | CY7C1354D | |
| Descripción | 9-Mbit (256K x 36) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1354D
9-Mbit (256K × 36) Pipelined SRAM with
NoBL™ Architecture
9-Mbit (256K × 36) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin-compatible and functionally equivalent to ZBT
■ Supports 200 MHz bus operations with zero wait states
❐ Available speed grade is 200 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 3.3 V power supply (VDD)
■ 3.3 V or 2.5 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 3.2 ns (for 200 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in non Pb-free 165-ball FBGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Logic Block Diagram – CY7C1354D
Functional Description
The CY7C1354D are 3.3 V, 256K × 36 synchronous pipelined
burst SRAM with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back-to-back
read/write operations with no wait states. The CY7C1354D are
equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature greatly improves the throughput
of data in systems that require frequent write/read transitions.
The CY7C1354D are pin compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354D) and a write enable (WE) input. All
writes are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
For a complete list of related documentation, click here.
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-88918 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 27, 2016
1 page  
CY7C1354D
Pin Definitions (continued)
Pin Name I/O Type
Pin Description
TCK
VDD
VDDQ
VSS
NC
JTAG-clock Clock input to the JTAG circuitry.
Power supply Power supply inputs to the core of the device.
I/O power Power supply for the I/O circuitry.
supply
Ground Ground for the device. Should be connected to ground of the system.
– No connects. This pin is not connected to the die.
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
ZZ
– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M, 288M,
576M, and 1G densities.
Input- ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Functional Overview
The CY7C1354D are synchronous-pipelined burst NoBL
SRAMs designed specifically to eliminate wait states during
write/read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (tCO) is 3.2 ns (200 MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[d:a] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and enables the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
register and to the data bus within 3.2 ns (200 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW for the device to drive out
the requested data. During the second clock, a subsequent
operation (read/write/deselect) can be initiated. Deselecting the
device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output tristates following the next clock rise.
Burst Read Accesses
The CY7C1354D has an on-chip burst counter that enables the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW to load a new address into the SRAM, as described
in Single Read Accesses. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wrap around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to A0–A16 is loaded into
the address register. The write signals are latched into the
control logic block.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
enables the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354D). In addition, the address
for the subsequent access (read/write/deselect) is latched into
Document Number: 001-88918 Rev. *B
Page 5 of 28
5 Page 
TAP Controller State Diagram
1 TEST-LOGIC
RESET
0
0 RUN-TEST/ 1
IDLE
SELECT
DR -SCA N
1
0
1
CA PTU R E-DR
0
SHIFT-DR 0
1
EXIT1-DR
1
0
PAUSE-DR 0
1
0
EXIT2-DR
1
U PDA TE-DR
10
CY7C1354D
SELECT
IR -SCA N
1
0
1
CA PTU R E-IR
0
SHIFT-IR
0
1
EXIT1-IR
1
0
PAUSE-IR 0
1
0
EXIT2-IR
1
U PDA TE-IR
10
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-88918 Rev. *B
Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CY7C1354D.PDF ] | |
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