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부품번호 | CY7C1356CV25 기능 |
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기능 | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
전체 30 페이지수
CY7C1354CV25
CY7C1356CV25
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin-compatible with and functionally equivalent to ZBT™
■ Supports 250-MHz bus operations with zero wait states
■ Available speed grades are 250, 200, and 166 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 2.5 V power supply (VDD)
■ Fast clock-to-output times
❐ 2.8 ns (for 250-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package and 165-ball FBGA
package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability–linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1354CV25/CY7C1356CV25[1] are 2.5 V,
256K × 36/512K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1354CV25/CY7C1356CV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1354CV25/CY7C1356CV25 are pin-compatible with and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354CV25 and BWa–BWb for
CY7C1356CV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.8
250
40
200 MHz
3.2
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05537 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2016
CY7C1354CV25
CY7C1356CV25
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Exit Order ............................................. 19
Boundary Scan Exit Order ............................................. 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC®Solutions ....................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Document Number: 38-05537 Rev. *Q
Page 4 of 35
4페이지 CY7C1354CV25
CY7C1356CV25
Pin Configurations (continued)
Figure 3. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1354CV25 (256K × 36)
123
A NC/576M
B NC/1G
A
A
CE1
CE2
C DQPc NC VDDQ
D
DQc
DQc
VDDQ
E
DQc
DQc
VDDQ
F
DQc
DQc
VDDQ
G
DQc
DQc
VDDQ
H NC NC NC
J
DQd
DQd
VDDQ
K
DQd
DQd
VDDQ
L
DQd
DQd
VDDQ
M
DQd
DQd
VDDQ
N DQPd NC VDDQ
P NC/144M NC/72M A
R MODE NC/36M A
123
A NC/576M
B NC/1G
A
A
CE1
CE2
C NC NC VDDQ
D
NC
DQb
VDDQ
E
NC
DQb
VDDQ
F
NC
DQb
VDDQ
G
NC
DQb
VDDQ
H NC NC NC
J DQb NC VDDQ
K DQb NC VDDQ
L DQb NC VDDQ
M DQb NC VDDQ
N DQPb NC VDDQ
P NC/144M NC/72M A
R MODE NC/36M A
4
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
5
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
7
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
CY7C1356CV25 (512K × 18)
4
BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
5
NC
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
7
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
NC/18M
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
NC/18M
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC/288M
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC/288M
A
Document Number: 38-05537 Rev. *Q
Page 7 of 35
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
CY7C1356CV25 | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM | Cypress Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |