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CY7C1460BV25 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 CY7C1460BV25은 전자 산업 및 응용 분야에서
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부품번호 CY7C1460BV25 기능
기능 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CY7C1460BV25 데이터시트, 핀배열, 회로
CY7C1460BV25
CY7C1462BV25
36-Mbit (1 M × 36/2 M × 18)
Pipelined SRAM with NoBL™ Architecture
36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades is 250 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
2.5 V core power supply
2.5 V I/O power supply
Fast clock-to-output times
2.6 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460BV25, CY7C1462BV25 available in Pb-free
165-ball FBGA package and CY7C1462BV25 available in
JEDEC-standard Pb-free 100-pin TQFP package
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1460BV25/CY7C1462BV25 are 2.5 V,
1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No
Bus Latency™ (NoBL logic, respectively. They are designed
to support unlimited true back-to-back read/write operations with
no wait states. The CY7C1460BV25/CY7C1462BV25 are
equipped with the advanced NoBL logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1460BV25/CY7C1462BV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1460BV25 and BWa–BWb for
CY7C1462BV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
For a complete list of related documentation, click here.
Logic Block Diagram – CY7C1460BV25
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BWa
BWb
BWc
BWd
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-74446 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 24, 2015




CY7C1460BV25 pdf, 반도체, 판매, 대치품
CY7C1460BV25
CY7C1462BV25
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
250 MHz
2.6
435
120
Unit
ns
mA
mA
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VVDSDSQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1462BV25
(2 M × 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPa
73 DQa
72 DQa
71 VSS
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSS
59 DQa
58 DQa
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document Number: 001-74446 Rev. *F
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CY7C1460BV25 전자부품, 판매, 대치품
CY7C1460BV25
CY7C1462BV25
Pin Definitions (continued)
Pin Name I/O Type
Pin Description
TMS
Test mode This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
select
synchronous
TCK
JTAG-clock Clock input to the JTAG circuitry.
VDD
VDDQ
Power supply Power supply inputs to the core of the device.
I/O power Power supply for the I/O circuitry.
supply
VSS
NC
NC/72M
NC/144M
NC/288M
NC/576M
NC/1G
ZZ
Ground
N/A
N/A
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
Not connected to the die. Can be tied to any voltage level.
N/A Not connected to the die. Can be tied to any voltage level.
N/A Not connected to the die. Can be tied to any voltage level.
N/A Not connected to the die. Can be tied to any voltage level.
N/A Not connected to the die. Can be tied to any voltage level.
Input- ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Functional Overview
The CY7C1460BV25/CY7C1462BV25 are
synchronous-pipelined burst NoBL SRAMs designed specifically
to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[x] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will three-state following the next clock rise.
Burst Read Accesses
The CY7C1460BV25/CY7C1462BV25 have an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Accesses section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and will wrap-around when incremented sufficiently.
A HIGH input on ADV/LD will increment the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (Read or Write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
Document Number: 001-74446 Rev. *F
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부품번호상세설명 및 기능제조사
CY7C1460BV25

36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM

Cypress Semiconductor
Cypress Semiconductor

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