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PDF CY7C1383KV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1383KV33 | |
| Descripción | 18-Mbit Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM (With ECC)
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC)
Features
■ Supports 133 MHz bus operations
■ 512K × 36 and 1M × 18 common I/O
■ 3.3 V core power supply (VDD)
■ 2.5 V or 3.3 V I/O supply (VDDQ)
■ Fast clock-to-output time
❐ 6.5 ns (133 MHz version)
■ Provides high performance 2-1-1-1 access rate
■ User selectable burst counter supporting interleaved or linear
burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ CY7C1381KV33/CY7C1381KVE33
available
in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball
FBGA package. CY7C1383KV33/CY7C1383KVE33 available
in JEDEC-standard Pb-free 100-pin TQFP.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option.
■ On-chip error correction code (ECC) to reduce soft error rate
(SER)
Functional Description
The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 are a 3.3 V, 512K × 36 and 1M × 18
synchronous flow through SRAMs, designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
chip enable (CE1), depth-expansion chip enables (CE2 and
CE3), burst control inputs (ADSC, ADSP, and ADV), write
enables (BWx, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an interleaved
burst sequence, while a LOW selects a linear burst sequence.
Burst accesses can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC)
inputs. Address advancement is controlled by the address
advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 operates from a +3.3 V core power supply
while all outputs operate with a +2.5 V or +3.3 V supply. All inputs
and outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
133 MHz 100 MHz Unit
6.5 8.5 ns
× 18 129
114 mA
× 36 149
134 mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97888 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 1, 2016
1 page  
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable)
CY7C1381KV33/CY7C1381KVE33 (512K × 36)
CY7C1383KV33/CY7C1383KVE33 (1M × 18)
Document Number: 001-97888 Rev. *E
Page 5 of 34
5 Page 
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Truth Table
The truth table for CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33 follows. [1, 2, 3, 4, 5]
Cycle Description
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
None
H X XL X
L X X X L–H Tri-State
None
L L XL
L
X X X X L–H Tri-State
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
None
None
None
None
External
External
External
L X HL
L L XL
X X HL
X X XH
L H LL
L H LL
L H LL
L
H
H
X
L
L
H
X X X X L–H Tri-State
L X X X L–H Tri-State
L X X X L–H Tri-State
X X X X X Tri-State
X X X L L–H Q
X X X H L–H Tri-State
L X L X L–H D
Read Cycle, Begin Burst
Read Cycle, Begin Burst
External
External
L H LL
L H LL
H
H
L X H L L–H Q
L X H H L–H Tri-State
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Next
Next
Next
Next
Next
Next
Current
X X XL
X X XL
H X XL
H X XL
X X XL
H X XL
X X XL
H
H
X
X
H
X
H
H L H L L–H Q
H L H H L–H Tri-State
H L H L L–H Q
H L H H L–H Tri-State
H L L X L–H D
H L L X L–H D
H H H L L–H Q
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Current
Current
X X XL
H X XL
H
X
H H H H L–H Tri-State
H H H L L–H Q
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Current
Current
Current
H X XL
X X XL
H X XL
X
H
X
H H H H L–H Tri-State
H H L X L–H D
H H L X L–H D
Notes
1. X = Don't Care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4.
The SRAM always initiates a read cycle when ADSP
rAeDmSaPinodrewr oitfhththeewarsitseecrtyiocnleo. f ADSC. As a result, OE
is asserted, regardless of the
must be driven HIGH prior to
sthtaetestoarftGoWf t,hBeWwErit,eocryBcWleXto. Walrloitewsthmeaoyuotcpcuutsr
only on subsequent clocks after
to tristate. OE is a don't care for
the
the
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-97888 Rev. *E
Page 11 of 34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1383KV33.PDF ] | |
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