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PDF CY7C1327G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1327G | |
| Descripción | 4-Mbit Pipelined Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1327G
4-Mbit (256K × 18) Pipelined Sync SRAM
4-Mbit (256K × 18) Pipelined Sync SRAM
Features
■ Registered inputs and outputs for pipelined operation
■ 256K × 18 common I/O Architecture
■ 3.3 V core power supply (VDD)
■ 2.5 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 3.5 ns (for 166-MHz device)
■ Provide high performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Offered in Pb-free 100-pin TQFP package
■ “ZZ” sleep mode option
Functional Description
The CY7C1327G SRAM integrates 256K × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as controlled
by the byte write control inputs. GW when active LOW causes all
bytes to be written.
The CY7C1327G operates from a +3.3 V core power supply
while all outputs also operate with a +3.3 V or a +2.5 V supply.
All inputs and outputs are JEDEC-standard JESD8-5-
compatible.
For a complete list of related documentation, click here.
Logic Block
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ B,DQP B
WRITE REGISTER
DQ A, DQP A
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ B,DQP B
WRITE DRIVER
DQ A, DQP A
WRITE DRIVER
MEMORY
ARRAY
SENSE OUTPUT
AMPS REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 21. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05519 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2016
1 page  
CY7C1327G
Pin Definitions (continued)
Name
I/O
Description
ADSC
Input- Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, A is captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized.
DQA, DQB,
DQPA,
DQPB
I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by “A”
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tristate
condition.
VDD
VSS
VDDQ
MODE
Power supply Power supply inputs to the core of the device.
Ground Ground for the device.
I/O ground Ground for the I/O circuitry.
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
NC,
NC/9M,
NC/18M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
– No connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
NC/576M and NC/1G are address expansion pins are not internally connected to the die.
Document Number: 38-05519 Rev. *Q
Page 5 of 24
5 Page 
CY7C1327G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [9, 10]
Description
IDD VDD operating supply current
ISB1 Automatic CE power-down
current – TTL inputs
ISB2 Automatic CE power-down
current – CMOS inputs
ISB3 Automatic CE power-down
current – CMOS inputs
ISB4 Automatic CE power-down
current – TTL inputs
Test Conditions
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
6 ns cycle,
166 MHz
7.5 ns cycle,
133 MHz
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
6 ns cycle,
166 MHz
7.5 ns cycle,
133 MHz
VDD = Max, device deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f=0
VDD = Max, device deselected, 6 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 166 MHz
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
VDD = Max, device deselected, All speeds
VIN VIH or VIN VIL, f = 0
Min
–
–
–
–
–
–
–
–
Max Unit
240 mA
225 mA
100 mA
90 mA
40 mA
85 mA
75 mA
45 mA
Capacitance
Parameter [11]
Description
CIN
CCLK
CI/O
Input capacitance
Clock input capacitance
Input/output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
100-pin TQFP
Max
5
5
5
Unit
pF
pF
pF
Thermal Resistance
Parameter [11]
Description
JA
JC
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
6.85
°C/W
°C/W
Note
11. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05519 Rev. *Q
Page 11 of 24
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