PDF CY7C1447AV33 Data sheet ( Hoja de datos )

Número de pieza	CY7C1447AV33
Descripción	36-Mbit Flow-Through SRAM
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY7C1447AV33 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Features ■ Supports 133-MHz bus operations ■ 1M x 36/2M x 18/512K x 72 common IO ■ 3.3V core power supply ■ 2.5V or 3.3V IO power supply ■ Fast clock-to-output times ❐ 6.5 ns (133-MHz version) ■ Provide high-performance 2-1-1-1 access rate ■ User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1441AV33, CY7C1443AV33 available in JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non-lead-free 165-ball FBGA package. CY7C1447AV33 available in Pb-free and non-lead-free 209-ball FBGA package ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ “ZZ” Sleep Mode option Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. 133 MHz 6.5 310 120 100 MHz 8.5 290 120 Unit ns mA mA Note 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation • 198 Champion Court Document #: 38-05357 Rev. G • San Jose, CA 95134-1709 • 408-943-2600 Revised May 09, 2008 [+] Feedback 1 page CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1441AV33 (1M x 36) 123 A NC/288M A CE1 B NC/144M A CE2 C DQPC NC VDDQ D DQC DQC VDDQ E DQC DQC VDDQ F DQC DQC VDDQ G DQC DQC VDDQ H NC NC NC J DQD DQD VDDQ K DQD DQD VDDQ L DQD DQD VDDQ M DQD DQD VDDQ N DQPD NC VDDQ P NC NC/72M A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A R MODE A A A TMS A0 TCK A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC/576M NC/1G DQB DQB DQB DQB NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC A DQA DQA DQA DQA DQPA A AA 123 A NC/288M A CE1 B NC/144M A C NC NC D NC DQB CE2 VDDQ VDDQ E NC DQB VDDQ F NC DQB VDDQ G NC DQB VDDQ H NC NC NC J DQB NC VDDQ K DQB NC VDDQ L DQB NC VDDQ M DQB NC VDDQ N DQPB NC VDDQ P NC NC/72M A R MODE A A CY7C1443AV33 (2M x 18) 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO A TMS A0 TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 AA A NC/576M NC/1G NC NC NC NC NC DQPA DQA DQA DQA DQA ZZ DQA DQA DQA DQA NC NC NC NC NC NC AA AA Document #: 38-05357 Rev. G Page 5 of 31 [+] Feedback 5 Page CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Partial Truth Table for Read/Write Function (CY7C1441AV33)[2, 7] Read Read Write Byte A (DQA, DQPA) Write Byte B(DQB, DQPB) Write Bytes A, B (DQA, DQB, DQPA, DQPB) Write Byte C (DQC, DQPC) Write Bytes C, A (DQC, DQA, DQPC, DQPA) Write Bytes C, B (DQC, DQB, DQPC, DQPB) Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) Write Byte D (DQD, DQPD) Write Bytes D, A (DQD, DQA, DQPD, DQPA) Write Bytes D, B (DQD, DQA, DQPD, DQPA) Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write Bytes D, B (DQD, DQB, DQPD, DQPB) Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Truth Table for Read/Write Function (CY7C1443AV33)[2] Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes Truth Table for Read/Write GW BWE BWB BWA HHXX H L HH HLHL HL LH HL L L LXXX Function (CY7C1447AV33)[2, 8] Read Read Write Byte x – (DQx and DQPx) Write All Bytes Write All Bytes GW BWE BWX H HX H L All BW = H H LL H L All BW = L L XX Notes 7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active. 8. BWx represents any byte write signal BW[A..H].To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled at the same time for any given write. Document #: 38-05357 Rev. *G Page 11 of 31 [+] Feedback 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet CY7C1447AV33.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C1447AV33	36-Mbit Flow-Through SRAM	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar