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PDF CY7C1441AV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1441AV25 | |
| Descripción | 36-Mbit Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1441AV25
CY7C1447AV25
36-Mbit (1M × 36/512K × 72)
Flow-Through SRAM
36-Mbit (1M × 36/512K × 72) Flow-Through SRAM
Features
■ Supports 133 MHz bus operations
■ 1M × 36/512K × 72 common I/O
■ 2.5 V core power supply
■ 2.5 V I/O power supply
■ Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed write
■ Asynchronous output enable
■ CY7C1441AV25 available in Pb-free 165-ball FBGA package.
CY7C1447AV25 available in non Pb-free 209-ball FBGA
package.
■ JTAG boundary scan for FBGA package
■ ZZ sleep mode option
Functional Description
The CY7C1441AV25/CY7C1447AV25 are 2.5 V, 1M × 36/512K × 72
Synchronous Flow-Through SRAMs, designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address pipelining Chip Enable (CE1), depth expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWx and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441AV25/CY7C1447AV25 allows either interleaved
or linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence and a LOW selects
a linear burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either ADSP or ADSC are active. Subsequent burst
addresses can be internally generated as controlled by the ADV.
The CY7C1441AV25/CY7C1447AV25 operates from a
+2.5 V core power supply while all outputs may operate with
either a +2.5 V supply. All inputs and outputs are
JEDEC-standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz
6.5
270
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75380 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 7, 2016
1 page  
CY7C1441AV25
CY7C1447AV25
Pin Configurations
12
A NC/288M A
B NC/144M A
C DQPC NC
D
DQC
DQC
E
DQC
DQC
F
DQC
DQC
G
DQC
DQC
H NC NC
J
DQD
DQD
K
DQD
DQD
L
DQD
DQD
M
DQD
DQD
N DQPD NC
P NC NC/72M
R MODE
A
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
CY7C1441AV25 (1M × 36)
4
BWC
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
5
BWB
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
7
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
A NC
A NC/576M
NC/1G
DQB
DQB
DQB
DQB
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
NC
A
DQA
DQA
DQA
DQA
DQPA
A
AA
Document Number: 001-75380 Rev. *F
Page 5 of 33
5 Page 
CY7C1441AV25
CY7C1447AV25
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1441AV25 follows. [6, 7]
Read
Function (CY7C1441AV25)
Read
Write Byte A (DQA, DQPA)
Write Byte B(DQB, DQPB)
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
Write Byte D (DQD, DQPD)
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
Write All Bytes
Write All Bytes
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BWB
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1447AV25 follows. [6, 8]
Function (CY7C1447AV25)
Read
Read
Write Byte x – (DQx and DQPx)
Write All Bytes
Write All Bytes
GW
BWE
BWx
HHX
H L All BW = H
HL L
H L All BW = L
LXX
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
8.
BWx represents any
at the same time for
byte
any
write
given
signal
write.
BWX.To
enable
any
byte
write
BWx,
a
logic
LOW
signal
should
be
applied
at
clock
rise.
Any
number
of
bye
writes
can
be
enabled
Document Number: 001-75380 Rev. *F
Page 11 of 33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1441AV25.PDF ] | |
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