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CY7C1360C 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 CY7C1360C은 전자 산업 및 응용 분야에서
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부품번호 CY7C1360C 기능
기능 9-Mbit Pipelined SRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CY7C1360C 데이터시트, 핀배열, 회로
CY7C1360C
CY7C1362C
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM
9-Mbit (256K × 36/512K × 18) Pipelined SRAM
Features
Supports bus operation up to 200 MHz
Available speed grades: 200 MHz, and 166 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply (VDD)
2.5 V/3.3 V I/O operation (VDDQ)
Fast clock-to-output times
3.0 ns (for 200 MHz device)
Provide high performance 3-1-1-1 access rate
User selectable burst counter supporting IntelPentium®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single cycle chip deselect
Available in Pb-free 100-pin TQFP package, non Pb-free
119-ball BGA package, and 165-ball FBGA package
TQFP available with 3-chip enable and 2-chip enable
IEEE 1149.1 JTAG-compatible boundary scan
Functional Description
The CY7C1360C/CY7C1362C SRAM integrates 256K × 36 and
512K × 18 SRAM cells with advanced synchronous peripheral
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
CchEip3[1e])n, abbulerst(CcEon1)t,rodl einppthu-tesxp(AanDsSioCn,
chip enables (CE2 and
ADSP, and ADV), write
enables (BWX, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 8 and Truth Table on
page 11 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1360C/CY7C1362C operate from a +3.3 V core power
supply while all outputs may operate with either a +2.5 or +3.3 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
200 MHz
3.0
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. CE3 is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05540 Rev. *R
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 9, 2016




CY7C1360C pdf, 반도체, 판매, 대치품
CY7C1360C
CY7C1362C
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enables - A Version)
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1360C
(256K × 36)
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSSQ
75 DQB
74 DQB
73 DQB
72 DQB
71 VSSQ
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSSQ
59 DQA
58 DQA
57 DQA
56 DQA
55 VSSQ
54 VDDQ
53 DQA
52 DQA
51 DQPA
Document Number: 38-05540 Rev. *R
Page 4 of 38

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CY7C1360C 전자부품, 판매, 대치품
CY7C1360C
CY7C1362C
Pin Configurations (continued)
Figure 4. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3 Chip Enables with JTAG)
123
A NC/288M
B NC/144M
A
A
CE1
CE2
C DQPC NC
VDDQ
D
DQC
DQC
VDDQ
E
DQC
DQC
VDDQ
F
DQC
DQC
VDDQ
G
DQC
DQC
VDDQ
H NC VSS NC
J
DQD
DQD
VDDQ
K
DQD
DQD
VDDQ
L
DQD
DQD
VDDQ
M
DQD
DQD
VDDQ
N DQPD NC
VDDQ
P NC NC/72M A
R MODE NC/36M A
CY7C1360C (256K × 36)
4 567
BWC
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
BWB
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC/18M
A1
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
A NC
A NC/576M
NC/1G
DQB
DQB
DQB
DQB
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
NC
A
DQA
DQA
DQA
DQA
DQPA
A
AA
Document Number: 38-05540 Rev. *R
Page 7 of 38

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