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PDF CY7C1338G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1338G | |
| Descripción | 4-Mbit Flow-Through Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1338G
4-Mbit (128K × 32) Flow-Through
Sync SRAM
4-Mbit (128K × 32) Flow-Through Sync SRAM
Features
■ 128K × 32 common I/O
■ 3.3 V core power supply (VDD)
■ 2.5 V or 3.3 V I/O supply (VDDQ)
■ Fast clock-to-output times
❐ 8.0 ns (100-MHz version)
■ Provide high-performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Offered in Pb-free 100-pin TQFP package
■ “ZZ” sleep mode option
Functional Description
The CY7C1338G is a 128K × 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
8.0 ns (100-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:D], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1338G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1338G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQD BYTE
WRITE REGISTER
DQC BYTE
WRITE REGISTER
DQB BYTE
WRITE REGISTER
DQA BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQD BYTE
WRITE REGISTER
DQC BYTE
WRITE REGISTER
DQB BYTE
WRITE REGISTER
DQA BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
INPUT
REGISTERS
Errata: For information on silicon errata, see "Errata" on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05521 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 8, 2016
1 page  
CY7C1338G
Pin Definitions (continued)
Name
DQs
VDD
VSS
VDDQ
VSSQ
MODE
NC
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
I/O Description
I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed
in a tri-state condition.
Power supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O power Power supply for the I/O circuitry.
supply
I/O ground Ground for the I/O circuitry.
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
No connects. Not Internally connected to the die.
– No connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to the die.
Document Number: 38-05521 Rev. *P
Page 5 of 23
5 Page 
CY7C1338G
Capacitance
Parameter [12]
Description
CIN
CCLK
CI/O
Input capacitance
Clock input capacitance
Input/Output capacitance
Thermal Resistance
Parameter [12]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
100-pin TQFP
Max
5
5
5
Unit
pF
pF
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
6.85
°C/W
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
OUTPUT
Z0 = 50
3.3 V
OUTPUT
RL = 50
5 pF
VT = 1.5 V
(a)
2.5 V I/O Test Load
INCLUDING
JIG AND
SCOPE
OUTPUT
Z0 = 50
2.5 V
OUTPUT
RL = 50
5 pF
VT = 1.25 V
(a)
INCLUDING
JIG AND
SCOPE
R = 317
R = 351
VDDQ
GND
ALL INPUT PULSES
10%
90%
1 ns
(b) (c)
R = 1667
R =1538
VDDQ
GND
10%
1ns
ALL INPUT PULSES
90%
(b) (c)
90%
10%
1 ns
90%
10%
1ns
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05521 Rev. *P
Page 11 of 23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CY7C1338G.PDF ] | |
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