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FM1808B 데이터시트 PDF




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부품번호 FM1808B 기능
기능 256-Kbit (32 K x 8) Bytewide F-RAM Memory
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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FM1808B 데이터시트, 핀배열, 회로
FM1808B
256-Kbit (32 K × 8) Bytewide F-RAM Memory
256-Kbit (32 K × 8) Bytewide F-RAM Memory
Features
256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32 K × 8
High-endurance 100 trillion (1014) read/writes
151-year data retention (see the Data Retention and
Endurance table)
NoDelay™ writes
Advanced high-reliability ferroelectric process
SRAM and EEPROM compatible
Industry-standard 32 K × 8 SRAM and EEPROM pinout
70-ns access time, 130-ns cycle time
Superior to battery-backed SRAM modules
No battery concerns
Monolithic reliability
True surface mount solution, no rework steps
Superior for moisture, shock, and vibration
Resistant to negative voltage undershoots
Low power consumption
Active current 15 mA (max)
Standby current 25 A (typ)
Voltage operation: VDD = 4.5 V to 5.5 V
Industrial temperature: –40 C to +85 C
28-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM1808B is a 32 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM1808B operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM1808B ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial
temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Logic Block Diagram
A14-0
A14-0
32 K x 8
F-RAM Array
CE
Control
WE Logic
OE
I/O Latch & Bus Driver
DQ 7-0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86209 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 4, 2015




FM1808B pdf, 반도체, 판매, 대치품
FM1808B
Device Operation
The FM1808B is a bytewide F-RAM memory logically organized
as 32,768 × 8 and accessed using an industry-standard parallel
interface. All data written to the part is immediately nonvolatile
with no delay. Functional operation of the F-RAM memory is the
same as SRAM type devices, except the FM1808B requires a
falling edge of CE to start each memory cycle. See the
Functional Truth Table on page 13 for a complete description of
read and write modes.
Memory Architecture
Users access 32,768 memory locations, each with 8 data bits
through a parallel interface. The complete 15-bit address
specifies each of the 32,768 bytes uniquely. The F-RAM array is
organized as 4092 rows of 8-bytes each. This row segmentation
has no effect on operation, however the user can group data into
blocks by its endurance characteristics as explained in the
Endurance section.
The cycle time is the same for read and write memory
operations. This simplifies memory controller logic and timing
circuits. Likewise the access time is the same for read and write
memory operations. When CE is deasserted HIGH, a pre-charge
operation begins, and is required of every memory cycle. Thus
unlike SRAM, the access and cycle times are not equal. Writes
occur immediately at the end of the access with no delay. Unlike
an EEPROM, it is not necessary to poll the device for a ready
condition since writes occur at bus speed.
It is the user’s responsibility to ensure that VDD remains within
datasheet tolerances to prevent incorrect operation. Also proper
voltage level and timing relationships between VDD and CE must
be maintained during power-up and power-down events. See
“Power Cycle Timing” on page 12.
Memory Operation
The FM1808B is designed to operate in a manner similar to other
bytewide memory products. For users familiar with BBSRAM,
the performance is comparable but the bytewide interface
operates in a slightly different manner as described below. For
users familiar with EEPROM, the differences result from the
higher write performance of F-RAM technology including
NoDelay writes and much higher write endurance.
Read Operation
A read operation begins on the falling edge of CE. At this time,
the address bits are latched and a memory cycle is initiated.
Once started, a full memory cycle must be completed internally
even if CE goes inactive. Data becomes available on the bus
after the access time is met.
After the address has been latched, the address value may be
changed upon satisfying the hold time parameter. Unlike an
SRAM, changing address values will have no effect on the
memory operation after the address is latched.
The FM1808B will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM1808B, writes occur in the same interval as reads. The
FM1808B supports both CE and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM1808B will not drive
the data bus regardless of the state of OE.
In a WE-controlled write, the memory cycle begins on the falling
edge of CE. The WE signal falls after the falling edge of CE.
Therefore, the memory cycle begins as a read. The data bus will
be driven according to the state of OE until WE falls. The CE and
WE controlled write timing cases are shown in the page 12.
Write access to the array begins asynchronously after the
memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access.
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Therefore, any operation including read or write
can occur immediately following a write. Data polling, a
technique used with EEPROMs to determine if a write is
complete, is unnecessary.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. All memory cycles
consist of a memory access and a pre-charge. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
The user determines the beginning of this operation since a
pre-charge will not begin until CE rises. However, the device has
a maximum CE LOW time specification that must be satisfied.
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle involves a
change of state. The memory architecture is based on an array
of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM1808B, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
accessed data is located in different rows. Regardless, F-RAM
Document Number: 001-86209 Rev. *E
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FM1808B 전자부품, 판매, 대치품
FM1808B
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS ........–1.0 V to + 7.0 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 7.0 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 4 kV
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ................. 300 V
Latch-up current ................................................... > 140 mA
Operating Range
Range
Industrial
Ambient Temperature (TA)
VDD
–40 C to +85 C
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VDD
IDD
ISB1
ISB2
ILI
ILO
VIH
VIL
VOH1
VOH2
VOL1
VOL2
Description
Power supply voltage
VDD supply current
Standby current (TTL)
Standby current (CMOS)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Test Conditions
Min Typ [1] Max
4.5 5.0 5.5
VDD = 5.5 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
VDD = 5.5 V, CE at VIH, All other pins are static
and at TTL levels (0.2 V or VDD – 0.2 V)
VDD = 5.5 V, CE at VIH, All other pins are static
and at CMOS levels (0.2 V or VDD – 0.2 V)
VIN between VDD and VSS
VOUT between VDD and VSS
2.0
– 0.3
– 15
– 1.8
25 50
– +1
– +1
– VDD + 0.3
– 0.8
IOH = –2.0 mA
IOH = –100 µA
IOL = 4.2 mA
IOL = 150 µA
2.4
VDD – 0.2
0.4
0.2
Unit
V
mA
mA
µA
µA
µA
V
V
V
V
V
V
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-86209 Rev. *E
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