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CY7C10612DV33 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 CY7C10612DV33은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 CY7C10612DV33 기능
기능 16-Mbit (1M x 16) Static RAM
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CY7C10612DV33 데이터시트, 핀배열, 회로
CY7C10612DV33
16-Mbit (1M × 16) Static RAM
16-Mbit (1M × 16) Static RAM
Features
High speed
tAA = 10 ns
Low active power
ICC = 175 mA at 100 MHz
Low CMOS standby power
ISB2 = 25 mA
Operating voltages of 3.3 ± 0.3 V
2.0 V data retention
Automatic Power-down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 54-pin TSOP II package
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
1M x 16
ARRAY
COLUMN
DECODER
Functional Description
The CY7C10612DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
To read from the device, take Chip Enables (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Truth Table on page 10 for a
complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C10612DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
For a complete list of related documentation, click here.
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-49315 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 29, 2016




CY7C10612DV33 pdf, 반도체, 판매, 대치품
CY7C10612DV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
VCC Relative to GND [2] ...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [2] ................................ –0.5 V to VCC + 0.5 V
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ..... ............................> 2001 V
Latch Up Current ................................................... > 200 mA
Operating Range
Range
Industrial
Ambient Temperature
–40 C to +85 C
VCC
3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH Output HIGH voltage
Min VCC, IOH = –4.0 mA
VOL Output LOW voltage
Min VCC, IOL = 8.0 mA
VIH Input HIGH voltage
VIL Input LOW voltage [2]
IIX
Input leakage current
GND VIN VCC
IOZ
Output leakage current
GND VOUT VCC, Output disabled
ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA,
CMOS levels
ISB1
Automatic CE power-down
Max VCC, CE VIH,
current – TTL inputs
VIN VIH or VIN VIL, f = fMAX
ISB2
Automatic CE power-down
Max VCC, CE VCC – 0.3 V,
current – CMOS Inputs
VIN VCC – 0.3 V, or VIN 0.3 V, f = 0
-10
Min Max
Unit
2.4 – V
– 0.4 V
2.0
–0.3
VCC + 0.3
0.8
V
V
–1 +1 A
–1 +1 A
– 175 mA
– 30 mA
– 25 mA
Capacitance
Parameter [3]
Description
CIN
COUT
Input capacitance
I/O capacitance
Thermal Resistance
Parameter [3]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
54-pin TSOP II Unit
6 pF
8 pF
Test Conditions
54-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit
board
24.18
C/W
5.40 C/W
Note
2. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-49315 Rev. *E
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CY7C10612DV33 전자부품, 판매, 대치품
CY7C10612DV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [10, 11]
ADDRESS
DATA I/O
tRRCC
tOHA
PREVIOUS DATA VALID
tAA
DATA OUT VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS
CE
OE
BHE, BLE
DATA I/O
VCC
SUPPLY
CURRENT
tACE
tDOE
tLZOE
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
50%
tRC
tHZOE
DATA OUT VALID
tHZCE
tHZBE
HIGH
IMPEDANCE
tPD
50%
IICCCC
IISSBB
Notes
10. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL.
11. WE is HIGH for read cycle.
12. Address valid before or similar to CE transition LOW.
Document Number: 001-49315 Rev. *E
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관련 데이터시트

부품번호상세설명 및 기능제조사
CY7C10612DV33

16-Mbit (1M x 16) Static RAM

Cypress Semiconductor
Cypress Semiconductor

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