PDF STK12C68 Data sheet ( Hoja de datos )

Número de pieza	STK12C68
Descripción	64 Kbit (8 K x 8) AutoStore nvSRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! STK12C68 64 Kbit (8 K x 8) AutoStore nvSRAM Features ■ 25 ns, 35 ns, and 45 ns access times ■ Hands off automatic STORE on power-down with external 68 µF capacitor ■ STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power-down ■ RECALL to SRAM initiated by software or power-up ■ Unlimited read, write, and recall cycles ■ 1,000,000 STORE cycles to QuantumTrap ■ 100 year data retention to QuantumTrap ■ Single 5 V + 10% operation ■ Commercial and industrial temperatures ■ 28-pin (330 mil) SOIC, 28-pin (300 mil) PDIP, 28-pin (600 mil) PDIP packages ■ 28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages ■ RoHS compliance Functional Description The Cypress STK12C68 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. For a complete list of related documentation, click here. Logic Block Diagram A5 A6 A7 A8 A9 A 11 A 12 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 Quantum Trap 128 X 512 STORE STATIC RAM ARRAY 128 X 512 RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 VCC VCAP POWER CONTROL STORE/ RECALL CONTROL HSB SOFTWARE DETECT -A0 A12 OE CE WE Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-51027 Rev. H • San Jose, CA 95134-1709 • 408-943-2600 Revised November 17, 2014 1 page STK12C68 Figure 3. AutoStore Inhibit Mode VCAP Vcc WE HSB Vss If the power supply drops faster than 20 us/volt before Vcc reaches VSWITCH, then a 2.2  resistor should be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP. AutoStore Inhibit Mode If an automatic STORE on power loss is not required, then VCC is tied to ground and +5 V is applied to VCAP (Figure 3). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK12C68 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control or the HSB pin. To enable or disable Autostore using an I/O port pin see Preventing Store on page 6. It is not permissible to change between these three options “on the fly”. Hardware STORE (HSB) Operation The STK12C68 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK12C68 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a Write to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. SRAM Read and Write operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK12C68 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM Read operations take place. If a Write is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. During any STORE operation, regardless of how it is initiated, the STK12C68 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK12C68 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. Hardware RECALL (Power-up) During power-up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. If the STK12C68 is in a Write state at the end of power-up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 k resistor is connected either between WE and system VCC or between CE and system VCC. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK12C68 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of Reads from specific addresses is used for STORE initiation, it is important that no other Read or Write accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following Read sequence is performed: 1. Read address 0x0000, Valid READ 2. Read address 0x1555, Valid READ 3. Read address 0x0AAA, Valid READ 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0F, Initiate STORE cycle The software sequence is clocked with CE controlled Reads or OE controlled Reads. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that Read cycles and not Write cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for Read and Write operation. Document Number: 001-51027 Rev. H Page 5 of 22 5 Page STK12C68 SRAM Write Cycle Parameter Cypress Parameter Alt tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [9,10] tLZWE [9] tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX Switching Waveforms ADDRESS CE WE Description Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write 25 ns Min Max 25 – 20 – 20 – 10 – 0– 20 – 0– 0– – 10 5– 35 ns Min Max 35 – 25 – 25 – 12 – 0– 25 – 0– 0– – 13 5– 45 ns Min Max 45 – 30 – 30 – 15 – 0– 30 – 0– 0– – 14 5– Unit ns ns ns ns ns ns ns ns ns ns Figure 9. SRAM Write Cycle 1: WE Controlled [11, 12] tWC tSCE tHA tAW tSA tPWE DATA IN DATA OUT ADDRESS PREVIOUS DATA tHZWE tSD DATA VALID HIGH IMPEDANCE tHD tLZWE Figure 10. SRAM Write Cycle 2: CE Controlled [11, 12] tWC tSA CE tSCE tHA WE DATA IN tAW tPWE tSD DATA VALID tHD DATA OUT HIGH IMPEDANCE Notes 10. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 11. HSB must be high during SRAM Write cycles. 12. CE or WE must be greater than VIH during address transitions. Document Number: 001-51027 Rev. *H Page 11 of 22 11 Page

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