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CY14B101MA 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 CY14B101MA은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CY14B101MA 자료 제공

부품번호 CY14B101MA 기능
기능 1-Mbit (128K x 8/64K x 16) nvSRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CY14B101MA 데이터시트, 핀배열, 회로
CY14B101KA
CY14B101MA
1-Mbit (128K × 8/64K × 16) nvSRAM with
Real Time Clock
1-Mbit (128K × 8/64K × 16) nvSRAM with Real Time Clock
Features
1-Mbit nonvolatile static random access memory (nvSRAM)
25 ns and 45 ns access times
Internally organized as 128K × 8 (CY14B101KA) or 64K × 16
(CY14B101MA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
RECALL to SRAM initiated on power-up or by software
High reliability
Infinite Read, Write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Real time clock (RTC)
Full featured real time clock
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Backup current of 0.35 µA (Typ)
Industry standard configurations
Single 3 V +20%, –10% operation
Industrial temperature
Packages
44-/54-pin thin small outline package (TSOP) Type II
48-pin shrink small outline package (SSOP)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B101KA/CY14B101MA combines a 1-Mbit
nvSRAM with a full featured real time clock in a monolithic
integrated circuit. The embedded nonvolatile elements
incorporate QuantumTrap technology producing the world’s
most reliable nonvolatile memory. The SRAM is read and written
an infinite number of times, while independent nonvolatile data
resides in the nonvolatile elements.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
For a complete list of related documentation, click here.
Logic Block Diagram[1, 2, 3]
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
R
O
W
D
E
C
O
D
E
R
Quatrum
Trap
1024 X 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
VCC
VCA
P
POWER
CONTROL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
VRTCbat
VRTCcap
HSB
A14 - A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I
N
P
U
T
B COLUMN I/O
U
F
F
E
R COLUMN DEC
S
A0 A1 A2 A3 A4 A10 A11
RTC
MUX
Xout
Xin
INT
A16- A0
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42880 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 22, 2016




CY14B101MA pdf, 반도체, 판매, 대치품
CY14B101KA
CY14B101MA
Pin Definitions
Pin Name I/O Type
Description
A0–A16
A0–A15
DQ0–DQ7
DQ0–DQ15
NC
Input Address inputs. Used to select one of the 131,072 Bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 65,536 Words of the nvSRAM for × 16 configuration.
Input/Output Bidirectional data I/O Lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional data I/O Lines for × 16 configuration. Used as input or output lines depending on operation.
No connect No connects. This pin is not connected to the die.
WE
Input
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE HIGH causes the I/O pins to tristate.
BHE
BLE
Xout[8]
Xin[8]
VRTCcap[8]
VRTCbat[8]
[8]
INT
Input
Input
Output
Byte High Enable, Active LOW. Controls DQ15–DQ8.
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
Crystal connection. Drives crystal on start up.
Input Crystal connection. For 32.768 kHz crystal.
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used.
Power supply Battery supplied backup RTC supply voltage. Left unconnected if VRTCcap is used.
Output
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
VCC
HSB
Ground Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB)
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Note
8. Left unconnected if RTC feature is not used.
Document Number: 001-42880 Rev. *O
Page 4 of 37

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CY14B101MA 전자부품, 판매, 대치품
CY14B101KA
CY14B101MA
Table 1. Mode Selection
CE WE
HX
LH
LL
LH
LH
LH
LH
OE
BHE, BLE[9]
A15–A0[10]
Mode
I/O Power
XX
X
Not selected Output high Z
Standby
LL
X
Read SRAM
Output data
Active
XL
X
Write SRAM
Input data
Active
L
X
0x4E38
Read SRAM
Output data
Active[11]
0xB1C7
Read SRAM
Output data
0x83E0
Read SRAM
Output data
0x7C1F
Read SRAM
Output data
0x703F
Read SRAM
Output data
0x8B45
AutoStore
Output data
Disable
L
X
0x4E38
Read SRAM
Output data
Active[11]
0xB1C7
Read SRAM
Output data
0x83E0
Read SRAM
Output data
0x7C1F
Read SRAM
Output data
0x703F
Read SRAM
Output data
0x4B46
AutoStore
Output data
Enable
L
X
0x4E38
Read SRAM
Output data
Active ICC2[11]
0xB1C7
Read SRAM
Output data
0x83E0
Read SRAM
Output data
0x7C1F
Read SRAM
Output data
0x703F
Read SRAM
Output data
0x8FC0
Nonvolatile
Output high Z
STORE
L
X
0x4E38
Read SRAM
Output data
Active[11]
0xB1C7
Read SRAM
Output data
0x83E0
Read SRAM
Output data
0x7C1F
Read SRAM
Output data
0x703F
Read SRAM
Output data
0x4C63
Nonvolatile
Output high Z
RECALL
Notes
9. BHE and BLE are applicable for × 16 configuration only.
10.
While there are 17 address lines on the CY14B101KA
modes. The remaining address lines are don’t care.
(16
address
lines
on
the
CY14B101MA),
only
the
13
address
lines
(A14A2)
are
used
to
control
software
11. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-42880 Rev. *O
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부품번호상세설명 및 기능제조사
CY14B101MA

1-Mbit (128K x 8/64K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor

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