Datasheet.kr   

XRT85L61 데이터시트 PDF




Exar에서 제조한 전자 부품 XRT85L61은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 XRT85L61 자료 제공

부품번호 XRT85L61 기능
기능 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
제조업체 Exar
로고 Exar 로고


XRT85L61 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 19 페이지수

미리보기를 사용할 수 없습니다

XRT85L61 데이터시트, 핀배열, 회로
xr
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
OCTOBER 2004
GENERAL DESCRIPTION
The XRT85L61 is an integrated E1, T1, 64KHz
Centralized Clock interface for T1 (1.544Mbps) 100,
E1 (2.048Mbps) 75or 120applications.
The XRT85L61 extracts either 2048kHz or 1544 kHz
clock signals from an E1 (2.048 MHz), T1 (1.544
Mhz) inputs respectively or 64 KHz, 8kHz or 400 Hz
clock signals from the 64kHz reference clock input.
The XRT85L61 includes an on-chip crystal-less jitter
attenuator with 32 bit FIFO that can either be enabled
or disabled.
FEATURES
Fully integrated single chip solution for E1,T1 or 64
kHz clock synchronization applications.
Extracts 2048 kHz, 1544 kHz clock and data
components
Extracts 64 KHz and 8 kHz, 400 Hz clock
information
Line Code Violation alarms
REV. 1.0.2
On-chip digital clock recovery circuit
Supports 75and 120(E1), 100(T1)
applications.
Crystal-less digital jitter attenuator with 32-bit FIFO
that can either be enabled or disabled
Receive loss of signal (RLOS) output
Meets Telcordia GR-1244-CORE Section 3.4.1 R3-
27 specification
Meets or exceeds T1 and E1 specifications in ITU
G.703, G.775
Single +3.3V Supply Operation
Logic inputs accept either 3.3 V or 5 V levels
28 pin TSSOP package
APPLICATIONS
Universal Clock Synchronization for G.703 Telecom
Formats
T1/E1 Line Receiver with Clock and Data Recovery
DSLAM
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61
RCLKINV
DATA_INV
DATAMUT
JAEN
Reference Inputs
MCLK1
(1.544 MHz for T1)
MCLK2
(2.048 MHz for E1
or 64 kbps)
Line Side
(T1 or E1 or 64 kbps input)
RTIP
RRING
S1
S2
S3
Master Clock
Generator
Rx
Equalizer
Peak Detector
and Slicer
Mode Select
T1, E1 or 64 kbps
Clock and
Data
Recovery
Jitter
Attenuator
LOS
Detector
Clock
Extractor
Line code
and clock
violation
Detector
RPOS
RNEG
RCLK
(64kHz,1544kHz or 2048kHz)
8 kHz (for 64 kbps)
400 Hz (for 64 kbps)
RCLK_LCV/AIS
8 kHz_LCV/BPV
400 Hz_LCV
RLOS
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




XRT85L61 pdf, 반도체, 판매, 대치품
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
xr
REV. 1.0.2
PIN DESCRIPTIONS
PIN #
1
SYMBOL
MCLK1
2 JAEN
3 MCLK2
4 JAVDD
5 JAGND
6 ICT
7 RTIP
8 RRING
9 AVDD
10 AGND
11 S1
TYPE
I
I
I
***
***
I
I
I
***
***
I
DESCRIPTION
Reference T1 Clock input:
This signal is an independent 1544 kHz clock with accuracy better than
+ 32 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in T1 mode. This signal must be
available for the device to operate.
Jitter Attenuator Enable:
Tie this pin “High” to enable the Jitter Attenuator. When enabled, a 32 bit
FIFO is included in the data path for all modes of operation.
NOTE: Internally Pulled down with 50 kresistor
Reference E1 and 64 kHz Clock Input:
This signal is an independent 2048 kHz clock with accuracy better than +
50 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in E1 and 64 kHz mode. This
signal must be available for the device to operate.
NOTE: To reduce intrinsic jitter when JA is enabled, it is recommended to
have reference clock with an accuracy of ± 25 ppm or better.
VDD for Jitter Attenuator (3.3V ± 5%)
Jitter Attenuator Ground
In circuit Testing
When this pin is grounded, all output pins are Tri-stated for testing pur-
poses.
NOTE: Internally Pulled up with 50 kresistor
Receive Positive Input
Receive Negative Input
Analog VDD (3.3V ± 5%)
Analog Ground
Mode Select
S1 S2 S3
MODE
0 0 0 64 kHz + 8 kHz
0 0 1 64kHz+8kHz+400Hz
0 1 0 E1 RZ
0 1 1 E1 NRZ
1 0 0 T1
1 0 1 T1 (output full width data)
1 1 0 E1 (output full width data)
1 1 1 Reserved
NOTE: T1 NRZ or E1 NRZ means the output data at RPOS and RNEG
are 1 RCLK wide.
3

4페이지










XRT85L61 전자부품, 판매, 대치품
xr
REV. 1.0.2
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
TABLE 3: T1 RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
PARAMETER
MIN
CABLE
LOSS
TYP
MAX
Receiver Sensitivity with PBRS
215-1 pattern
9
6
UNIT
TEST CONDITION
dB 9dB Cable Loss
dB 6dB Cable Loss + 6dB Flat Loss
NOTE: 0dB = 3.0Vp
4
dB 4dB Cable Loss + 8dB Flat Loss
TABLE 4: 64KBITS/SEC RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
PARAMETER
MIN TYP MAX
UNIT
TEST CONDITION
Receiver Sensitivity with Bipo-
lar Violation Encoded "All 1’s"
Pattern
NOTE: 0dB = 1.0Vp
9
6
4
dB 9dB Cable Loss
dB 6dB Cable Loss + 6dB Flat Loss
dB 4dB Cable Loss + 8dB Flat Loss
FIGURE 3. TIMING DIAGRAM FOR SYSTEM INTERFACE
RClk tr
RClk tf
RClk
RPOS/RNEG
RZ Mode
RPOS/RNEG
NRZ Mode
tRp tRp
tDS
tDH
6

7페이지


구       성 총 19 페이지수
다운로드[ XRT85L61.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
XRT85L61

BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR

Exar
Exar

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵