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PALCE16V8H-15 데이터시트 PDF




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부품번호 PALCE16V8H-15 기능
기능 EE CMOS Universal Programmable Array Logic
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PALCE16V8H-15 데이터시트, 핀배열, 회로
-
PALCE16V8H-15/25
EE CMOS Universal Programmable Array Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
Pin, function and fuse-map compatible with all
20-pln GAL® devices
Electrically erasable CMOS technology
provides reconfigurable logic and full
testability
High speed CMOS technology
- 15-ns propagation delay for "-15" version
- 25-ns propagation delay for "-25" version
Direct plug-in replacement for the PAL16R8
series and most of the PAL1OH8 series
Outputs programmable as registered or
combinatorial in any combination
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL® device built with
low-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocells provide a universal device
architecture. ThePALCE16V8 will directly replace the
PAL16R8 and PAL1OH8 series devices, with the excep-
tion of the PAL16C1.
Device logic is automatically configured according to the
user's design specification. Design is simplified by
PALASM design software, allowing automatic creation
of a programming file based on Boolean or state equa-
tions. PALASM software also verifies the design and
can provide test vectors for the finished device. Pro-
gramming can be accomplished on standard PAL
device programmers.
BLOCK DIAGRAM
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP and PLCC
packages
Programmable on standard device
programmers
Supported by PALASM® software
Fully tested for high programming and
functional yields and high reliability
The PALCE16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased elec-
trically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The su m of these products
feeds the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial with an active-
HIGH or active-LOW output. The output configuration is
determined by two global bits and one local bit control-
ling four multiplexers in each macrocell.
PALCE16V8 Block Diagram
12015-0011<
Publication # 12015 Rev. A
Issue Date: April 1989
Amendment
iii




PALCE16V8H-15 pdf, 반도체, 판매, 대치품
FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. It has eight
independently configurable macrocells (MCo•• MC7).
The macrocells can be configured as registered output,
combinatorial output, combinatorial 1/0 or dedicated in-
put. The programming matrix implements a program-
mable AND logic array, which drives a fixed OR logic ar-
ray. Buffers for device inputs have complementary out-
puts to provide user-programmable input signal polarity.
Pins 1 and 11 serve either as array inputs or as clock
(CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to VCC or
GND. Product terms with all bits unprogrammed (dis-
connected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are
automatically configured from the user's design specifi-
cation, which can be in a numberof formats. The design
specification is processed by development software to
verify the deSign and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.
The user is given two design options with the
PALCE16V8. First, it can be programmed as a standard
PAL device from the PAL16R8 and PAL1OH8 series.
The PAL programmer manufacturer will supply device
codes for the standard PAL device architectures to be
used with the PALCE16V8. The programmer will pro-
gram the PALCE16V8 in the corresponding architec-
ture. This allows the user to use existing standard PAL
device files without making any changes to them. This
includes JEDEC files. Alternatively, the device can be
programmed as a PALCE16V8. Here the user must use
the PALCE16V8 device code. This option allows full
utilization of the macrocell.
r-----------------~ 11
10
.------------1 01
00
II0 x
SLO x
From Adjacent
Macrocell
"In macrocells MCo and MC7, SG1 is replaced by SGO on the feedback multiplexer.
PALCE16V8 Macrocell
12015-<l04A
vi PALCE16V8H-15/25

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PALCE16V8H-15 전자부품, 판매, 대치품
Power-Up Reset
All flip-flops power up to a logic LOW for predictable sys-
tem initialization. Outputs of the PALCE16V8 will de-
pend onwhetherthey are selected as registered orcom-
binatorial. If registered is selected, the output will be
LOW. If combinatorial is selected, the output is a func-
tion of the logic.
Electronic Signature Word
An electronic signature word is provided in the
PALCE16V8 device. It consists of 64 bits of programm-
able memory that can contain user-defined data. The
signature data is always available to the user independ-
ent of the security bit.
Programming and Erasing
The PALCE16V8 can be programmed on standard logic
programmers. Approved programmers are listed in this
data sheet.
The PALCE16V8 may be erased to reset a previously
configured device back to its virgin state. Bulk erase is
automatically performed by the programming hardware.
No special erase operation is required.
Security Bit
A security bit is provided on the PALCE16V8 as a deter-
rent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
of the programmed pattern by a device programmer, se-
curing proprietary designs from competitors. However,
programming and verification are also defeated by the
security bit. The bit can only be erased in conjunction
with the array during a bulk erase cycle.
Basic PAL Device Notation
The mUlti-input gates in the PAL device's programmable
AND gate array are simplified in the logic diagrams. The
PAL device notation for an AND gate, called a product
term in a PAL device, is shown below.
* *I I I I D- A*D
ABC 0 E F
12015-006A
Figure 3. PAL Device AND Gate
This is equivalent to the standard logic notation below.
~==D--AD
12015-007A
Figure 4. Standard AND Gate
Each vertical line in the PAL device is a potential input to
the AND gate. At each crosspoint is a programmable
bit, which provides a potential connection in the pro-
grammed state. The Xs in the diagram indicate a con-
nection at the crosspoint.
In electrically erasable devices the crosspoints are origi-
nally disconnected. They are either connected or left
open during device programming.
Multiplexers in the PAL device logic diagrams use a sim-
ple notation for maximum clarity. A 2:1 multiplexer that
selects X when the control is LOW and Y when the
control is HIGH is shown below.
xz
y
xz
y
12015-00SA
Figure 5. PAL Device Multiplexer
Notice that the control is operated by a programmable
cell that is initially disconnected from GND, floating to
Vcc, selecting the "1" path through the multiplexer.
When the cell is programmed, it is connected to GND
selecting the "0" path through the multiplexer.
PALCE16V8H-15/25
ix

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PALCE16V8H-15

EE CMOS Universal Programmable Array Logic

Advanced Micro Devices
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