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PDF EL4585 Data sheet ( Hoja de datos )
| Número de pieza | EL4585 | |
| Descripción | Horizontal Genlock | |
| Fabricantes | Intersil | |
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®
Data Sheet
September 3, 2009
EL4585
FN7175.4
Horizontal Genlock, 8FSC
The EL4585 is a PLL (Phase Lock Loop) sub-system,
designed for video applications and also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS-compatible pixel clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 sync separator. An
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video
timing such as VTR head switching. The lock detector output
indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards by external
selection of three control pins. These four ratios have been
selected for common video applications including 8FSC,
6FSC, 27MHz (CCIR 601 format) and square picture
elements used in some workstation graphics. To generate
4FSC, 3FSC, 13.5MHz (CCIR 601 format) etc., use the
EL4584, which does not have the additional divide-by-two
stage of the EL4585.
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
FREQUENCIES AND DIVISORS
FUNCTION
Divisor (Note 4)
6FSC CCIR 601 SQUARE
(Note 1) (Note 2) (Note 3)
1702
1728
1888
8FSC
2270
PAL FOSC (MHz)
Divisor (Note 4)
26.602
1364
27.0
1716
29.5
1560
35.468
1820
NTSC FOSC (MHz) 21.476
27.0
24.546 28.636
NOTES:
1. 6FSC frequencies do not yield integer divisors.
2. CCIR 601 divisors yield 1440 pixels in the active portion of each
line for NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL.
4. Divisor does not include ÷ 2 block.
Features
• 36MHz, general purpose PLL
• 8FSC timing (use the EL4584 for 4FSC)
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User-controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed popular TV scan rate clock divisors
• Single 5V, low current operation
• Pb-Free Available (RoHS Compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing
Ordering Information
PART
NUMBER
PART
MARKING
PACKAGE
PKG.
DWG. #
EL4585CN
EL4585CN
16 Ld PDIP
E16.3
EL4585CS
EL4585CS 16 Ld SOIC MDP0027
EL4585CS-T7* EL4585CS 16 Ld SOIC MDP0027
EL4585CS-T13* EL4585CS 16 Ld SOIC MDP0027
EL4585CSZ
(Note 5)
EL4585CSZ 16 Ld SOIC
(Pb-free)
MDP0027
EL4585CSZ-T7* EL4585CSZ 16 Ld SOIC
(Note 5)
(Pb-free)
MDP0027
EL4585CSZ-T13* EL4585CSZ 16 Ld SOIC
(Note 5)
(Pb-free)
MDP0027
*Please refer to TB347 for details on reel specifications.
NOTES:
5. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet
or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. For 3FSC and 4FSC clock frequency operation, see EL4584
datasheet.
Demo Board
A demo PCB is available for this product.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Timing Diagrams
EL4585
H-SYNC
(INPUT)
~200ns ± 50ns
EXT. DIV.
(INPUT OR
OUTPUT)
PLL LOCKED CONDITION (PHASE ERROR = 0)
HSYNC
EXT. DIV
-
+
CHARGE
PUMP -OFF
~200ns
t0
tH
+
θE = tθtH × 360°
tH = HSYNC PERIOD
tθ = PHASE ERROR PERIOD
OFF
OUT OF LOCK CONDITION
Test Circuit
+
VOUT
-
3
0.1µF
VIN
10mVRMS
5
TEST CIRCUIT 1
5 FN7175.4
September 3, 2009
5 Page 
EL4585
.
FIGURE 12. TYPICAL LOOP FILTER
LC LOOP FILTER COMPONENTS (APPROXIMATE)
FREQUENCY
R2
R3
C3
C4
(MHz)
(kΩ) (kΩ) (µF) (µF)
26.602
100
39
0.01 0.001
27.0 100 39 0.01 0.001
29.5 100 43 0.01 0.001
35.468
100
51
0.01 0.001
21.476
100
30
0.01 0.001
24.546
100
36
0.01 0.001
28.636
100
43
0.01 0.001
XTAL LOOP FILTER COMPONENTS (APPROXIMATE)
FREQUENCY
R2
R3
C3
C4
(MHz)
(kΩ)
(MΩ)
(pF)
(pF)
26.602 100 4.3 68 6.8
27.0 100 4.3 68 6.8
29.5 100 4.3 68 6.8
35.468 100 4.3 68 6.8
21.476 100 4.3 68 6.8
24.546 100 4.3 68 6.8
28.636 100 4.3 68 6.8
PCB Layout Considerations
It is highly recommended that power and ground planes be
used in layout. The oscillator and filter sections constitute a
feedback loop and thus care must be taken to avoid any
feedback signal influencing the oscillator except at the
control input. The entire oscillator/filter section should be
surrounded by copper ground to prevent unwanted
influences from nearby signals. Use separate paths for
analog and digital supplies, keeping the analog (oscillator
section) as short and free from spurious signals as possible.
Careful attention must be paid to correct bypassing. Keep
lead lengths short and place bypass caps as close to the
supply pins as possible. If laying out a PCB to use discrete
components for the VCO section, care must be taken to
avoid parasitic capacitance at the OSC pins 3 and 5, and
FILTER out (pin 7). Remove ground and power plane copper
above and below these traces to avoid making a capacitive
connection to them. It is also recommended to enclose the
oscillator section within a shielded cage to reduce external
influences on the VCO, as they tend to be very sensitive to
“hand waving” influences, the LC variety being more
sensitive than crystal controlled oscillators. In general, the
higher the operating frequency, the more important these
considerations are. Self contained VCXO or VCO modules
are already mounted in a shielding cage and therefore do
not require as much consideration in layout. Many crystal
manufacturers publish informative literature regarding use
and layout of oscillators which should be helpful.
11 FN7175.4
September 3, 2009
11 Page | ||
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| PDF Descargar | [ Datasheet EL4585.PDF ] | |
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