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PDF EL5421 Data sheet ( Hoja de datos )
| Número de pieza | EL5421 | |
| Descripción | Quad 12MHz Rail-to-Rail Input-Output Buffer | |
| Fabricantes | Intersil | |
| Logotipo |  |
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August 2, 2007
EL5421
FN7198.2
Quad 12MHz Rail-to-Rail Input-Output
Buffer
The EL5421 is a quad, low power, high voltage rail-to-rail
input-output buffer. Operating on supplies ranging from 5V to
15V, while consuming only 500µA per channel, the EL5421
has a bandwidth of 12MHz (-3dB). The EL5421 also
provides rail-to-rail input and output ability, giving the
maximum dynamic range at any supply voltage.
The EL5421 also features fast slewing and settling times, as
well as a high output drive capability of 30mA (sink and
source). These features make the EL5421 ideal for use as
voltage reference buffers in Thin Film Transistor Liquid
Crystal Displays (TFT-LCD). Other applications include
battery power, portable devices and anywhere low power
consumption is important.
The EL5421 is available in a space saving 10 Ld MSOP
package and operates over a temperature range of -40°C to
+85°C.
Features
• 12MHz -3dB bandwidth
• Unity gain buffer
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) = 500µA
• High slew rate = 10V/µs
• Rail-to-rail operation
• “Mini” SO package (MSOP)
• Pb-free plus anneal available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Electronics notebooks
• Electronics games
• Personal communication devices
Pinout
EL5421
(10 LD MSOP)
TOP VIEW
• Personal digital assistants (PDA)
• Portable instrumentation
• Wireless LANs
VOUTA 1
VINA 2
VS+ 3
VINB 4
VOUTB 5
10 VOUTD
9 VIND
8 VS-
7 VINC
6 VOUTC
• Office automation
• Active filters
• ADC/DAC buffers
Ordering Information
PART
NUMBER
PART
MARKING
PACKAGE
PKG. DWG. #
EL5421CY
F
10 Ld MSOP MDP0043
EL5421CY-T7* F
10 Ld MSOP MDP0043
EL5421CY-T13* F
10 Ld MSOP MDP0043
EL5421CYZ
(Note)
BCAAA
10 Ld MSOP MDP0043
(Pb-Free)
EL5421CYZ-T7* BCAAA
(Note)
10 Ld MSOP MDP0043
(Pb-Free)
EL5421CYZ-T13* BCAAA
(Note)
10 Ld MSOP MDP0043
(Pb-Free)
*Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Elantec is a registered trademark of Elantec Semiconductor, Inc. Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Typical Performance Curves
EL5421
1800
1600
1400
VS=±5V
TA=25°C
1200
1000
800
600
400
200
0
TYPICAL
PRODUCTION
DISTRIBUTION
INPUT OFFSET VOLTAGE (mV)
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
70
VS=±5V
60
50
40
30
20
10
0
TYPICAL
PRODUCTION
DISTRIBUTION
INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
10
VS=±5V
5
0
-5
-50
0
50 100 150
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
2.0
VS=±5V
0.0
-2.0
-50 0 50 100 150
TEMPERATURE (°C)
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
4.97
4.96
4.95
4.94
4.93
VS=±5V
IOUT=5mA
-50 0
50 100
TEMPERATURE (°C)
150
FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE
-4.91
VS=±5V
-4.92 IOUT=-5mA
-4.93
-4.94
-4.95
-4.96
-4.97
-50
0 50 100
TEMPERATURE (°C)
150
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
5 FN7198.2
August 2, 2007
5 Page 
EL5421
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
0.5 486mW
0.4
0.3
JA =2M0S6°OCP/W10
0.2
0.1
0
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Unused Buffers
It is recommended that any unused buffer have the input tied
to the ground plane.
Driving Capacitive Loads
The EL5421 can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking increase. The
buffers drive 10pF loads in parallel with 10k with just 1.5dB
of peaking, and 100pF with 6.4dB of peaking. If less peaking
is desired in these applications, a small series resistor
(usually between 5 and 50) can be placed in series with
the output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
"snubber" circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150 and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current or reduce the gain.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5421 can provide gain at high frequency. As with any
high-frequency device, good printed circuit board layout is
necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to ground,
a 0.1µF ceramic capacitor should be placed from VS+ to pin
to VS- pin. A 4.7µF tantalum capacitor should then be
connected in parallel, placed in the region of the buffer. One
4.7µF capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
11 FN7198.2
August 2, 2007
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet EL5421.PDF ] | |
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