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PDF TW2816 Data sheet ( Hoja de datos )
| Número de pieza | TW2816 | |
| Descripción | 4 Channel Video Decoders | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TW2816 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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NOT RECOMMENDED FOR NEW DESIGNS
Contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
TW2816
4 Channel Video Decoders
For Security Applications
Data Sheet
Information may change without notice.
.
January 31, 2011
FN7736.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Block Diagram
VIN1
ADC
4H Comb
Video Decoder
VIN2
ADC
4H Comb
Video Decoder
VIN3
ADC
4H Comb
Video Decoder
VIN4
ADC
4H Comb
Video Decoder
VD1[7:0]
VD2[7:0]
VD3[7:0]
VD4[7:0]
MPP1
MPP2
MPP3
MPP4
CLKPO
CLK54I
CLKNO
SCLK
SDAT
IRQ
5 FN7736.0
January 31, 2011
5 Page 
Sync Processing
The sync processor of TW2816 detects horizontal and vertical synchronization signals in the
composite. The TW2816 utilizes proprietary technology for locking to weak, noisy, or unstable
signals such as those from on-air signal and fast forward or backward of VCR system.
Automatic Gain Control and Clamping
A patented digital gain and clamp control circuit restores the ac coupled video signal to a fixed dc
level. The clamping circuit provides line-by-line restoration of the video pedestal level to a fixed dc
reference voltage. In no AGC mode, the gain control circuit adjusts only the video sync gain to
achieve desired sync amplitude so that the active video is bypassed regardless of the gain control.
But when AGC mode is enabled, both active video and sync are adjusted by the gain control. The
range of AGC is from –6dB to 18dB approximately. Additionally, an automatic white peak control
circuit is included to prevent saturation in the case of abnormal proportion between sync and white
peak level.
Horizontal Sync Processing
The horizontal synchronization processing contains a sync separator, a PLL and the related
decision logic. The horizontal sync separator detects the horizontal sync by examining low-pass
filtered video input whose level is lower than a threshold. Additional logic is also used to avoid false
detection on glitches. The horizontal PLL locks onto the extracted horizontal sync in all conditions to
provide jitter free image output. In case the horizontal sync is missing, the PLL is on free running
status that matches the standard raster frequency.
Vertical Sync Processing
The vertical sync separator detects the vertical synchronization pattern in the input video signals.
The field status is determined at vertical synchronization time. When the location of the detected
vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field start.
Otherwise, it indicates an even field.
11 FN7736.0
January 31, 2011
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TW2816.PDF ] | |
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