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TW2828 데이터시트 PDF




Intersil에서 제조한 전자 부품 TW2828은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 TW2828 기능
기능 HD/SD DVR Video Port Expander
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TW2828 데이터시트, 핀배열, 회로
HD/SD DVR Video Port Expander
TW2828
TW2828 is a display and recording MUX chip with HD
SPOT capability designed to work with popular H.264
CODEC on the market today. TW2828 provides a clean
and cost effective MUX solution to the multi-channel PC
HD DVR marketplace. On the embedded DVR market,
using TW2828 in conjunction with a host SOC can
deliver the most cost effective solution on the market.
Digital Input Ports
Four byte interleaved BT.656 ports each supporting
up to 4 SD (108 MHz) and 4 960H (144 MHz) signals
for a total of 16 SD video input signals
Five frame interleaved BT.1120 ports, each
supporting up to 148.5 MHz for a total of 20 HD
signals. One port (PB5) is shared with GPIO port
Four frame interleaved BT.656 ports (shared with the
lower half of the BT.1120 port), supporting up to 16
SD (or 960H) signals in frame/field interleaved
format
Supports input resizing, cutting and cropping
Supports channel cascading
Display Controller
Supports popular sizes such as: 1920x1080i50, i60,
1920x1080p50 or p60,720p50 and p60
Max pixel clock: 148.5MHz
Capable of displaying up to 36 SD Channels by using
byte interleaved inputs and frame interleaved inputs
Motion Box (MD) on all live channels
Selectable Weave/2D de-interlacing method for video
quality enhancement
Up/down scaler for arbitrary windows size
OSD display layer for title and channel ID
Single Box Display for highlighting and Mouse/Cursor
Overlay
BT.1120 or digital RGB output interface
Analog VGA output (shared with SPOT output)
Digital Output Port
One BT. 1120 port to the backend chip
Digital RGB output (shared with BT.1120 port)
SPOT digital output (BT.656) through record (shared)
pins with all the channels
SPOT and Record Interface
Two SPOT port with Integrated DAC
1/4/9/16 format for each SD (or 960H) and HD
channels
Supports anti-rolling display
Similar recording functions like TW2880
Motion Detection
16 SD/WD1 (960H) mode size 16x12
720p HD mode 40x36
1080i HD mode 60x27
1080p HD mode 60x54
DDR2 Interface
Supports 16-bit DDR2 memories running up to
333MHz
Supports DRAM density from 512Mb to 1Gb
Host Interface
8-bit parallel host interface or I2C slave interface
(shared pin)
Four I2C slave addresses on two separate pins for
cascaded operation
IRQs
Package
18mmx18mm 409 LFBGA
March 27, 2013
FN8291.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




TW2828 pdf, 반도체, 판매, 대치품
TW2828
PB Channel ID Dec PB5 VOS 0x3B0 ......................................................................... 64
PB Channel ID Dec PB5 FOS 0x3B1 ......................................................................... 64
PB Channel ID Dec PB5 HOS 0x3B2......................................................................... 64
PB Channel ID Dec PB5 MID_VAL 0x3B3 ................................................................. 64
Live Video Channel 1~4 No Video Register 0x3BD ................................................... 65
Live Video Channel 1~4 Non Standard Register 0x3C1 ............................................ 65
Live Video Channel Control Register 0x3C5 .............................................................. 65
Live Video Channel System Select Register 0x3C6................................................... 66
test pattern Video FORMAT Select Register 0x3CC.................................................. 66
test pattern Video FORMAT Select Register 0x3CD.................................................. 66
test pattern Video FORMAT Select Register 0x3Ce .................................................. 66
Live/Record Channel Select Register 0x3D2 ............................................................. 67
Live/Record Set Select Register 0x3DA ..................................................................... 67
Digital Video Input (Type 2)............................................................................................................ 68
Introduction ............................................................................................................................. 68
Features .................................................................................................................................. 68
Input Port Architecture ............................................................................................................ 68
BT.656 Mode Architecture ............................................................................................. 69
Functions ....................................................................................................................... 70
Register Descriptions .............................................................................................................. 71
Toggle Field Signal Enable Register 0x357 ............................................................... 71
PB1 Vertical Target Size LSB Register 0x358 ........................................................... 71
PB1 and PB2 Vertical Target Size MSB Register 0x359............................................ 71
PB2 Vertical Target Size LSB Register 0x35A ........................................................... 71
PB1 Vertical Source Size LSB Register 0x35E .......................................................... 71
PB1 and PB2 Vertical Source Size MSB Register 0x35F .......................................... 72
PB2 Vertical Source Size LSB Register 0x360 .......................................................... 72
PB1 Horizontal Scaler Target LSB Register 0x364 .................................................... 72
PB1 and PB2 Horizontal Target Size MSB Register 0x365 ....................................... 72
PB2 Horizontal Scaler Target LSB Register 0x366 .................................................... 72
PB1 Horizontal Scaler Source LSB Register 0x36A................................................... 72
PB1 and PB2 Horizontal Source Size MSB Register 0x36B ...................................... 73
PB2 Horizontal Scaler Source LSB Register 0x36C .................................................. 73
PB MISC Control Register 0x371 ............................................................................... 73
PB YC Component Switch Register 0x372 ................................................................ 74
PB Test Input Control Register 0x373 ........................................................................ 75
PB Channel ID Dec Read Bus PB1 Byte 10x372....................................................... 75
PB Channel ID Dec Read Bus PB1 Byte 2 0x373...................................................... 76
PB Channel ID Dec Read Bus PB1 Byte 3 0x374...................................................... 77
Horizontal Delay for Playback Port 1 Register 0x3B5 ................................................ 77
Vertical Delay for Playback Port 1 Register 0x3B6 .................................................... 78
PB Channel ID Dec Read Bus PB1 Byte 4 0x3C7 ..................................................... 78
PB Channel ID Dec Read Bus PB1 Byte 5 0x3C8 ..................................................... 78
PB In_PB_Test Register 0x3DC................................................................................. 79
PB In_PB_Test Pattern Generator Color Bar Shift Volume 0x3DD ........................... 80
PB Channel ID Dec PB1 Ctrl 0x3DE .......................................................................... 80
PB Channel ID Dec PB1 VOS 0x3DF......................................................................... 80
PB Channel ID Dec PB1 FOS 0x3E0 ......................................................................... 81
PB Channel ID Dec PB1 HOS 0x3E1......................................................................... 81
PB Channel ID Dec PB1 MID_VAL 0x3E2 ................................................................. 81
PB Channel ID Dec PB2 VAL 0x3E3.......................................................................... 81
PB Channel ID Dec PB2 VOS 0x3E4 ......................................................................... 82
PB Channel ID Dec PB2 VOS 0x3E5 ......................................................................... 82
PB Channel ID Dec PB2 HOS 0x3E6......................................................................... 82
PB Channel ID Dec PB2 MID_VAL 0x3E7 ................................................................. 82
PB Channel ID Dec PB3 VAL 0x3E8.......................................................................... 82
PB Channel ID Dec PB3 VOS 0x3E9 ......................................................................... 83
PB Channel ID Dec PB3 VOS 0x3EA......................................................................... 83
4

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TW2828 전자부품, 판매, 대치품
TW2828
PHY DQ Offset Register LOW 0x153 ...................................................................... 119
PHY DQ Offset Register HIGH 0x154 ...................................................................... 119
PHY Gatelvl_init_ratio Register LOW 0x155 ............................................................ 119
PHY Gatelvl_init_ratio Register MID 0x156.............................................................. 120
PHY Gatelvl_init_ratio Register HIGH 0x157 ........................................................... 120
PHY Gatelvl_init_mode Register 0x157 .................................................................. 120
PHY Gatelvl_num_of_dq0 Register 0x158 .............................................................. 120
PHY Ctrl Slave Ratio Register LOW 0x159 .............................................................. 120
PHY Ctrl Slave Ratio Register HIGH 0x15A............................................................. 120
PHY Ctrl Slave Delay Register 0x15B ..................................................................... 120
PHY Ctrl Slave Force Register 0x15C..................................................................... 121
PHY Rd Dqs Slave Ratio Register 1 0x15D ............................................................. 121
PHY Rd Dqs Slave Ratio Register 2 0x15e.............................................................. 121
PHY Rd Dqs Slave Ratio Register 3 0x15f............................................................... 121
PHY Rd Dqs Slave Delay Register LOW 0x160....................................................... 121
PHY Rd Dqs Slave Delay Register MID 0x161 ........................................................ 121
PHY Rd Dqs Slave Delay Register HIGH 0x162...................................................... 122
PHY FIFO We Slave Ratio Register LOW 0x163..................................................... 122
PHY FIFO We Slave Ratio Register MID 0x164 ...................................................... 122
PHY FIFO We Slave Ratio Register HIGH 0x165 .................................................... 122
PHY FIFO We In Delay Register LOW 0x166 .......................................................... 122
PHY FIFO We In Delay Register MID 0x167............................................................ 122
PHY FIFO We In Delay Register HIGH 0x168 ......................................................... 123
PHY Wr Data Slave Ratio Register LOW 0x169 ...................................................... 123
PHY Wr Data Slave Ratio Register MID 0x16A ....................................................... 123
PHY Wr Data Slave Ratio Register HIGH 0x16B ..................................................... 123
PHY Wr Data Slave Delay Register LOW 0x16C..................................................... 123
PHY Wr Data Slave Delay Register MID 0x16d ....................................................... 123
PHY Wr Data Slave Delay Register HIGH 0x16E .................................................... 123
PHY Wr Data Slave Force Register 0x16E ............................................................. 124
PHY Wr Rl Delay Register 0x16F............................................................................ 124
PHY Rd Rl Delay Register 0x170 ............................................................................ 124
PHY DLL Lock Diff Register 0x171.......................................................................... 124
PHY MISC 0 Register 0x172 ................................................................................... 124
PHY MISC 1 Register 0x173 ................................................................................... 125
PHY MISC 2 Register 0x174 ................................................................................... 125
PHY MISC 3 Register 0x176 ................................................................................... 126
Rdlvl_fifowein_ratio Register LOW 0x177 ................................................................ 126
Rdlvl_fifowein_ratio Register MID 0x178.................................................................. 126
Rdlvl_fifowein_ratio Register HIGH 0x179 ............................................................... 126
DLL_slave_value Register LOW 0x17A ................................................................... 126
DLL_slave_value Register HIGH 0x17B................................................................... 127
In_delay_value Register LOW 0x17C....................................................................... 127
In_delay_value Register HIGH 0x17D...................................................................... 127
Out_delay_value Register LOW 0x17E .................................................................... 127
Out_delay_value Register HIGH 0x17F ................................................................... 127
Lock_state Register 0x17F ...................................................................................... 127
Phy_ctrl_dll_slave_value Register LOW 0x180....................................................... 128
Phy_ctrl_dll_slave_value Register HIGH 0x181....................................................... 128
Phy_ctrl_In_delay_value Register LOW 0x182 ........................................................ 128
Phy_ctrl_In_delay_value Register HIGH 0x183 ....................................................... 128
Phy_ctrl_Out_delay_value Register LOW 0x184 ..................................................... 128
Phy_ctrl_Out_delay_value Register HIGH 0x185 .................................................... 128
Phy_ctrl_Lock_state Register 0x185 ....................................................................... 128
Rd_dqs_slave_dll_value Register LOW 0x186 ........................................................ 129
Rd_dqs_slave_dll_value Register MID 0x187.......................................................... 129
Rd_dqs_slave_dll_value Register HIGH 0x188 ....................................................... 129
Wr_data_slave_dll_value Register LOW 0x189 ....................................................... 129
7

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