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ISL23345 데이터시트 PDF




Intersil에서 제조한 전자 부품 ISL23345은 전자 산업 및 응용 분야에서
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부품번호 ISL23345 기능
기능 Low Voltage Digitally Controlled Potentiometer
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ISL23345 데이터시트, 핀배열, 회로
Quad, 256 Tap, Low Voltage Digitally ControlledNORTECROEMCOMMENMDEENDIDSERLD2E3PF3LO2A5RCNEEMWENDTEPSAIGRNTS
Potentiometer (XDCP™)
ISL23345
The ISL23345 is a volatile, low voltage, low noise, low power,
256 tap, quad digitally controlled potentiometer (DCP) with an
I2C Businterface. It integrates four DCP cores, wiper switches
and control logic on a monolithic CMOS integrated circuit.
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly
written to and read by the user. The contents of the WRi
controls the position of the wiper. When powered on, the wiper
of each DCP will always commence at mid-scale (128 tap
position).
The low voltage, low power consumption, and small package
of the ISL23345 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23345 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23345 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
Applications
• Power supply margining
• Trimming sensor circuits
• Gain adjustment in battery powered instruments
• RF power amplifier bias compensation
Features
• Four potentiometers per package
• 256 resistor taps
• 10k 50kor 100ktotal resistance
• I2C serial interface
- No additional level translator for low bus supply
- Three address pins allow up to eight devices per bus
• Maximum supply current without serial bus activity
(standby)
- 5µA @ VCC and VLOGIC = 5V
- 2µA @ VCC and VLOGIC = 1.7V
• Shutdown Mode
- Forces the DCP into an end-to-end open circuit and RWi is
connected to RLi internally
- Reduces power consumption by disconnecting the DCP
resistor from the circuit
• Power supply
- VCC = 1.7V to 5.5V analog power supply
- VLOGIC = 1.2V to 5.5V I2C bus/logic power supply
• Wiper resistance: 70typical @ VCC = 3.3V
• Power-on preset to mid-scale (128 tap position)
• Extended industrial temperature range: -40°C to +125°C
• 20 Ld TSSOP or 20 QFN packages
• Pb-free (RoHS compliant)
10000
8000
6000
4000
2000
0
0 64 128 192
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10kDCP
256
VREF
RH1
1 DCP
of
ISL23345
RW1
RL1
-
+
ISL28114
VREF_M
FIGURE 2. VREF ADJUSTMENT
June 21, 2011
FN7872.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners




ISL23345 pdf, 반도체, 판매, 대치품
ISL23345
Absolute Maximum Ratings
Supply Voltage Range
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper Current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 6kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
20 Ld TSSOP Package (Notes 4, 6) . . . . . .
85
33
20 Ld QFN Package (Notes 5, 7) . . . . . . . .
40
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is taken at the package top center.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 20) TYP (Note 8) (Note 20) UNITS
RTOTAL RH to RL Resistance
W option
U option
10 k
50 k
T option
100 k
RH to RL Resistance Tolerance
-20 ±2 +20 %
End-to-End Temperature Coefficient W option
125 ppm/°C
U option
65 ppm/°C
T option
45 ppm/°C
VRH, VRL
RW
DCP Terminal Voltage
Wiper Resistance
CH/CL/CW Terminal Capacitance
VRH or VRL to GND
RH - floating, VRL = 0V, force IW current to the
wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V
VCC = 1.7V
See “DCP Macro Model” on page 9
0
VCC
70 200
580
32/32/32
V
pF
ILkgDCP
Noise
Leakage on DCP Pins
Resistor Noise Density
Voltage at pin from GND to VCC
Wiper at middle point, W option
-0.4 < 0.1 0.4 µA
16 nV Hz
Wiper at middle point, U option
49 nV Hz
Wiper at middle point, T option
61 nV Hz
Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point
-65 dB
PSRR Power Supply Reject Ratio
Wiper output change if VCC change ±10%;
wiper at middle point
-75 dB
4 FN7872.0
June 21, 2011

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ISL23345 전자부품, 판매, 대치품
ISL23345
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 20) TYP (Note 8) (Note 20) UNITS
tDCP Wiper Response Time
SCL rising edge of the acknowledge bit after data
byte to wiper new position (Changes from 10% to
90% FS)
W, U, T options specified top to bottom
0.4
1.5
3.5
µs
µs
µs
tShdnRec DCP Recall Time from Shutdown Mode
SCL rising edge of the acknowledge bit after ACR
data byte to wiper recalled position and RH
connection
1.5
µs
VCC,VLOGIC VCC ,VLOGIC Ramp Rate
Ramp
(Note 21)
Ramp monotonic at any level
0.01 50 V/ms
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX
(Note 20) (Note 8) (Note 20) UNITS
VIL
VIH
Hysteresis
VOL
Cpin
fSCL
tsp
Input LOW Voltage
Input HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage
SDA, SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
VLOGIC > 2V
VLOGIC < 2V
IOL = 3mA, VLOGIC > 2V
IOL = 1.5mA, VLOGIC < 2V
Any pulse narrower than the max spec is
suppressed
-0.3
0.7 x VLOGIC
0.05 x VLOGIC
0.1 x VLOGIC
0
0.3 x VLOGIC
VLOGIC + 0.3
0.4
V
V
V
V
V
0.2 x VLOGIC V
10 pF
400 kHz
50 ns
tAA
SCL Falling Edge to SDA Output
SCL falling edge crossing 30% of VLOGIC, until
Data Valid
SDA exits the 30% to 70% of VLOGIC window
tBUF Time the Bus Must be Free Before SDA crossing 70% of VLOGIC during a STOP
1300
the Start of a New Transmission condition, to SDA crossing 70% of VLOGIC during
the following START condition
900 ns
ns
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
Clock LOW Time
Measured at the 30% of VLOGIC crossing
Clock HIGH Time
Measured at the 70% of VLOGIC crossing
START Condition Set-up Time
SCL rising edge to SDA falling edge; both crossing
70% of VLOGIC
START Condition Hold Time
From SDA falling edge crossing 30% of VLOGIC to
SCL falling edge crossing 70% of VLOGIC
Input Data Set-up Time
From SDA exiting the 30% to 70% of VLOGIC
window, to SCL rising edge crossing 30% of
VLOGIC
Input Data Hold Time
From SCL falling edge crossing 70% of VLOGIC to
SDA entering the 30% to 70% of VLOGIC window
STOP Condition Set-up Time
From SCL rising edge crossing 70% of VLOGIC, to
SDA rising edge crossing 30% of VLOGIC
STOP Condition Hold Time for Read From SDA rising edge to SCL falling edge; both
or Write
crossing 70% of VLOGIC
1300
600
600
600
100
0
600
1300
ns
ns
ns
ns
ns
ns
ns
ns
7 FN7872.0
June 21, 2011

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관련 데이터시트

부품번호상세설명 및 기능제조사
ISL23345

Low Voltage Digitally Controlled Potentiometer

Intersil
Intersil
ISL23348

Low Voltage Digitally Controlled Potentiometer

Intersil
Intersil

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