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PDF ACTS74MS Data sheet ( Hoja de datos )
| Número de pieza | ACTS74MS | |
| Descripción | Radiation Hardened Dual D Flip Flop | |
| Fabricantes | Intersil | |
| Logotipo |  |
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TM ACTS74MS
January 1996
Radiation Hardened Dual D
Flip Flop with Set and Reset
itle
CTS
MS)
b-
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al D
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thor
ey-
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ter-
mi-
n-
ctor,
dia-
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ed,
,
d
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ass
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRFF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96713 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14,
LEAD FINISH C
TOP VIEW
R1 1
D1 2
CP1 3
S1 4
Q1 5
Q1 6
GND 7
14 VCC
13 R2
12 D2
11 CP2
10 S2
9 Q2
8 Q2
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ)
Description
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with
Set(s) and Reset (R). The logic level at data input is transferred to the
output during the positive transition of the clock. The Set and Reset are
independent from the clock and accomplished by a low level on the
appropriate input.
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP3-F14,
LEAD FINISH C
TOP VIEW
R1
D1
CP1
S1
Q1
Q1
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
R2
D2
CP2
S2
Q2
Q2
The ACTS74MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
14 Lead Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9671301VCC
5962F9671301VXC
ACTS74D/Sample
ACTS74K/Sample
ACTS74HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
25oC
25oC
25oC
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
Spec Number 518787
File Number 3382.1
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet ACTS74MS.PDF ] | |
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