Datasheet.kr   

HS-1840AEH 데이터시트 PDF




Intersil에서 제조한 전자 부품 HS-1840AEH은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 HS-1840AEH 자료 제공

부품번호 HS-1840AEH 기능
기능 Rad-Hard 16 Channel BiCMOS Analog Multiplexer
제조업체 Intersil
로고 Intersil 로고


HS-1840AEH 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 7 페이지수

미리보기를 사용할 수 없습니다

HS-1840AEH 데이터시트, 핀배열, 회로
Rad-Hard 16 Channel BiCMOS Analog Multiplexer with
High-Z Analog Input Protection
HS-1840ARH, HS-1840AEH,
HS-1840BRH, HS-1840BEH
The HS-1840ARH, HS-1840AEH, HS-1840BRH and HS-1840BEH are
radiation hardened, monolithic 16 channel multiplexers constructed
with the Intersil Rad-Hard Silicon Gate, bonded wafer, Dielectric
Isolation process. They are designed to provide a high input impedance
to the analog source if device power fails (open), or the analog signal
voltage inadvertently exceeds the supply by up to 35V, regardless of
whether the device is powered on or off. Excellent for use in redundant
applications, since the secondary device can be operated in a standby
unpowered mode affording no additional power drain. More
significantly, a very high impedance exists between the active and
inactive devices preventing any interaction. One of sixteen channel
selections is controlled by a 4-bit binary address plus an Enable-Inhibit
input which conveniently controls the ON/OFF operation of several
multiplexers in a system. All inputs have electrostatic discharge
protection. The HS-1840ARH, HS-1840AEH, HS-1840BRH and
HS-1840BEH are processed and screened in full compliance with
MIL-PRF-38535 and QML standards. The devices are available in a
28 Ld SBDIP and a 28 Ld Ceramic Flatpack.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are contained in
SMD 5962-95630.
Features
• Electrically screened to SMD # 5962-95630
• QML qualified per MIL-PRF-38535 requirements
• Pin-to-pin for Intersil’s HS-1840RH and HS-1840/883S
• Improved radiation performance
- Gamma dose () 3x105RAD(Si)
• Improved rDS(ON) Linearity
• Improved access time 1.5µs (Max) over temp and post rad
• High analog input impedance 500Mduring power loss (open)
35V input overvoltage protection (power on or off)
• Dielectrically isolated device islands
• Excellent in Hi-Rel redundant systems
• Break-before-make switching
• No latch-up
Pin Configuration
HS1-1840ARH, HS1-1840AEH, HS1-1840BRH,
HS1-1840BEH
(28 LD SBDIP) CDIP2-T28
TOP VIEW
+VS 1
NC 2
NC 3
IN 16 4
IN 15 5
IN 14 6
IN 13 7
IN 12 8
IN 11 9
IN 10 10
IN 9 11
GND 12
(+5VS) VREF 13
ADDR A3 14
28 OUT
27 -VS
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
20 IN 2
19 IN 1
18 ENABLE
17 ADDR A0
16 ADDR A1
15 ADDR A2
HS9-1840ARH, HS9-1840AEH, HS9-1840BRH, HS9-1840BEH
(28 LD FLATPACK) CDFP3-F28
TOP VIEW
+VS
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
(+5VS) VREF
ADDR A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 OUT
27 -VS
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
20 IN 2
19 IN 1
18 ENABLE
17 ADDR A0
16 ADDR A1
15 ADDR A2
May 23, 2013
FN4355.6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2009-2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




HS-1840AEH pdf, 반도체, 판매, 대치품
HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH
Burn-In/Life Test Circuits
+VS
GND
F4
1
R
2
3
4
5
6
7
8
9
10
11
12
13
14
R
28
27
26 R
25
24
23
22
21
20
19
18
17 F1
16
15 F3
-VS
F5
F2
+VS
GND
VR
1
R
2
3
4
5
6
7
8
9
10
11
12
13
14
R
R
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
-VS
NOTE:
VS+ = +15.5V ±0.5V, VS- = -15.5V ±0.5V.
R = 1kΩ ±5%.
C1 = C2 = 0.01µF ±10%, 1 EACH PER SOCKET, MINIMUM.
D1 = D2 = 1N4002, 1 EACH PER BOARD, MINIMUM.
INPUT SIGNALS:
SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK ±10%.
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
NOTE:
R = 1kΩ ±5%, 1/4W.
C1 = C2 = 0.01µF MINIMUM, 1 EACH PER SOCKET, MINIMUM.
VS+ = 15.5V ±0.5V, VS- = -15.5V ±0.5V, VR = 15.5 ±0.5V
FIGURE 2. .STATIC BURN-IN TEST CIRCUIT
Irradiation Circuit
HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH
+15V
NC
NC
+1V
+5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27 -15V
26
25
24
23
22
21
20
19
18
17
16
15
1k
NOTE:
3. All irradiation testing is performed in the 28 lead CERDIP package.
4 FN4355.6
May 23, 2013

4페이지










HS-1840AEH 전자부품, 판매, 대치품
HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
e
-A-
PIN NO. 1
ID AREA
A
A
-B- D
S1
b
E1
0.004 M H A - B S D S
0.036 M H A - B S D S
Q
A
-C-
SEATING AND
BASE PLANE
E -D-
L E2
E3 E3
c1 LEAD FINISH
L
C
-H-
BASE
METAL
(c)
b1
NOTES:
MM
(b)
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)
28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.740
- 18.80
3
E
0.460
0.520 11.68
13.21
-
E1
-
0.550
- 13.97
3
E2 0.180 - 4.57
-
-
E3 0.030 - 0.76
-
7
e 0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
2
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1 0.00
- 0.00
-
6
M
-
0.0015
-
0.04
-
N 28
28 -
Rev. 0 5/18/94
7 FN4355.6
May 23, 2013

7페이지


구       성 총 7 페이지수
다운로드[ HS-1840AEH.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
HS-1840AEH

Rad-Hard 16 Channel BiCMOS Analog Multiplexer

Intersil
Intersil

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵