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PDF HS-565BEH Data sheet ( Hoja de datos )
| Número de pieza | HS-565BEH | |
| Descripción | Monolithic Digital-to-Analog Converter | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Radiation Hardened High Speed, Monolithic
Digital-to-Analog Converter
HS-565BRH, HS-565BEH
The HS-565BRH, HS-565BEH are fast, radiation hardened
12-bit current output, digital-to-analog converters. This part
replaces the HS-565ARH, which is no longer available. The
monolithic chips include a precision voltage reference,
thin-film R-2R ladder, reference control amplifier and twelve
high-speed bipolar current switches.
The Intersil Dielectric Isolation process provides latch-up free
operation while minimizing stray capacitance and leakage
currents, to produce an excellent combination of speed and
accuracy. Also, ground currents are minimized to produce a
low and constant current through the ground terminal, which
reduces error due to code-dependent ground currents.
HS-565BRH, HS-565BEH die are laser trimmed for a
maximum integral nonlinearity error of0.25 LSB at +25°C. In
addition, the low noise buried zener reference is trimmed both
for absolute value and minimum temperature coefficient.
Specifications for Rad Hard QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96755.
Features
• Electrically Screened to SMD # 5962-96755
• QML Qualified per MIL-PRF-38535 Requirements
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad (Si) (Max)
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
• Low Gain Drift
(Max., DAC Plus Reference) . . . . . . . . . . . . . . . . . . 50ppm/°C
• 0.75 LSB Accuracy Guaranteed Over Temperature
(0.125 LSB Typical at +25°C)
Applications
• High Speed A/D Converters
• Precision Instrumentation
• Signal Reconstruction
REF OUT VCC
43
+
-
6
REF IN
5
REF GND
19.95k
10V
IREF
0.5mA
3.5k
+
-
3k
BIP.
OFF.
8
9.95k
DAC
IO
(4X IREF
X CODE)
11
20V SPAN
5k
10
10V SPAN
5k 9
OUT
2.5k
7
-VEE
12
PWR
GND
24 . . . 13
MSB LSB
FIGURE 1. FUNCTIONAL DIAGRAM
May 7, 2012
FN4607.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2003, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
HS-565BRH, HS-565BEH
Settling Time
This is a challenging measurement, in which the result depends
on the method chosen, the precision and quality of test
equipment and the operating configuration of the DAC (test
conditions). As a result, the different techniques in use by
converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test method before using the specified
settling time as a basis for design.
The approach used for several years at Intersil calls for a strobed
comparator to sense final perturbations of the DAC output
waveform. This gives the LSB a reasonable magnitude (814mV)
for the HS-565BRH, HS-565BEH, which provides the comparator
with enough overdrive to establish an accurate 0.50 LSB
window about the final settled value. Also, the required test
conditions simulate the DACs environment for a common
application - use in a successive approximation A/D converter.
Considerable experience has shown this to be a reliable and
repeatable way to measure settling time.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (tON) or on-to-off
(tOFF). The slower of the two cases is specified, as measured
from 50% of the digital input transition to the final entry within a
window of ±0.50 LSB about the settled value. Four
measurements characterize a given type of DAC:
(a) tON, to final value +0.50 LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50 LSB). For example, refer to Figures 4A and 4B for
the measurement of case (d).
Procedure
As shown in Figure 4B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
• Adjust the delay on generator number 2 for a tX of several
microseconds. This assures that the DAC output has settled to
its final wave.
• Switch on the LSB (+5V)
• Adjust the VLSB supply for 50% triggering at COMPARATOR
OUT. This is indicated by traces of equal brightness on the
oscilloscope display as shown in Figure 4B. Note DVM reading.
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before, and
note DVM reading. One LSB equals one tenth the difference in
the DVM readings noted above.
• Adjust the VLSB supply to reduce the DVM reading by 5 LSBs
(DVM reads 10X, so this sets the comparator to sense the final
settled value minus 0.50 LSB). Comparator output disappears.
• Reduce generator number 2 delay until comparator output
reappears, and adjust for “equal brightness”.
• Measure tX from scope as shown in Figure 4B. Settling time
equals tX + tD, i.e., tX + 15ns.
MODE
Unipolar (See Figure 2)
Bipolar (See Figure 3)
OUTPUT
RANGE
0 to +10V
0 to +5V
10V
5V
2.5V
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
PIN 10
TO
PIN 11
TO
RESISTOR
(R)
APPLY
INPUT CODE
VO Pin 10 1.43k
All 0’s
All 1’s
VO Pin 9
1.1k
All 0’s
All 1’s
NC VO 1.69k All 0’s
All 1’s
VO Pin 10 1.43k
All 0’s
All 1’s
VO Pin 9
1.1k
All 0’s
All 1’s
CALIBRATION
ADJUST
R1
R2
R1
R2
R3
R4
R3
R4
R3
R4
TO SET VO
0V
+9.99756V
0V
+4.99878V
-10V
+9.99512V
-5V
+4.99756V
-2.5V
+2.49878V
5 FN4607.4
May 7, 2012
5 Page | ||
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| PDF Descargar | [ Datasheet HS-565BEH.PDF ] | |
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