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PDF AOZ3046PI Data sheet ( Hoja de datos )
| Número de pieza | AOZ3046PI | |
| Descripción | 4A Synchronous Buck Regulator | |
| Fabricantes | ALPHA & OMEGA | |
| Logotipo |  |
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AOZ3046PI
EZBuck™ 4 A Synchronous Buck Regulator
General Description
The AOZ3046PI is a high efficiency, simple to use, 4 A
synchronous buck regulator. The AOZ3046PI operates
from a 7.5 V to 18 V input voltage range, and provides up
to 4 A of continuous output current with an output voltage
adjustable down to 0.8 V.
The AOZ3046PI comes in an exposed pad SO-8
package and is rated over a -40 °C to +85 °C operating
ambient temperature range.
Features
7.5 V to 18 V operating input voltage range
350 µA quiescent current typical applications
60 mΩ internal high-side switch and 30 mΩ internal
low-side switch (at 12 V)
PEM (pulse energy mode) enables 82 % plus
efficiency with IOUT = 10 mA (VIN = 12 V, VOUT = 5 V)
Up to 95 % efficiency
Internal soft start
Output voltage adjustable to 0.8 V
4 A continuous output current
500 kHz PWM operation
Cycle-by-cycle current limit
Pre-bias start-up
Short-circuit protection
Thermal shutdown
Exposed pad SO-8 package
Applications
Point of load DC/DC converters
LCD TV
Set top boxes
DVD and Blu-ray players/recorders
Cable modems
Typical Application
VIN
C1
10µF
RC
CC
CCC
VIN VCC
VOUT
EN
AOZ3046
COMP
LX
FB
AGND
PGND
L1 5.8µH
R1
R2
VOUT
C2, C3
22µF
Rev. 2.0 October 2014
Figure 1. 5 V, 4 A Synchronous Buck Regulator, Fs = 500 KHz
www.aosmd.com
Page 1 of 14
1 page  
AOZ3046PI
Typical Performance Characteristics
Circuit of Figure 1. TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V, L = 4.7 µH unless otherwise specified.
Light Load Operation
Full Load Operation
VLX
10V/div
Vo ripple
50mV/div
1µs/div
IL
0.5A/div
Vin ripple
0.2V/div
Light Load to Heavy Load Operation
2µs/div
Heavy Load to Light Load Operation
VLX
2V/div
VLX
10V/div
IL
1A/div
Vo ripple
50mV/div
Vin ripple
0.5V/div
VLX
10V/div
20µs/div
Short Circuit Protection
Vo
0.2V/div
IL
2A/div
VLX
10V/div
20µs/div
Short Circuit Recovery
Vo
0.2V/div
IL
2A/div
VLX
10V/div
20ms/div
Vo
2V/div
IL
5A/div
20ms/div
Vo
2V/div
IL
5A/div
Rev. 2.0 October 2014
www.aosmd.com
Page 5 of 14
5 Page 
AOZ3046PI
Thermal Management and Layout
Considerations
In the AOZ3046PI buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pad, to the filter inductor, to the output capacitor and
load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from the inductor,
to the output capacitors and load, to the low side
NMOSFET. Current flows in the second loop when the
low side NMOSFET is on.
In PCB layout, minimizing the area of the two loops will
reduce the noise of the circuit and improves efficiency.
A ground plane is strongly recommended to connect the
input capacitor, the output capacitor, and the PGND pin
of the AOZ3046PI.
In the AOZ3046PI buck regulator circuit, the major power
dissipating components are the AOZ3046PI and the
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power:
Ptotal_loss = VIN IIN – VO IO
The power dissipation of the inductor can be
approximately calculated by the output current and DCR
value of the inductor:
Pinductor_loss = IO2 Rinductor 1.1
The actual junction temperature can be calculated by the
power dissipation in the AOZ3046PI and the thermal
impedance from junction to ambient:
Tjunction = Ptotal_loss–Pinductor_loss JA
The maximum junction temperature of the AOZ3046PI is
150 ºC, which limits the maximum load current capability.
The thermal performance of the AOZ3046PI is strongly
affected by the PCB layout. Care should be taken during
the design process to ensure that the IC will operate
under the recommended environmental conditions.
Layout Considerations
The AOZ3046PI is an exposed pad SO-8 package.
Several layout tips are listed for the best electric and
thermal performance.
1. The exposed pad (LX) is connected to the internal
PFET and NFET drains. Connected a large copper
plane to the LX pin to help thermal dissipation.
2. Do not use a thermal relief connection to the VIN pin
or the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
3. The input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and only connect
them at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current trace from the LX pad to L to Co to
the PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal trace away from the LX pad.
VOUT
PGND 1
VIN 2
AGND 3
VCC 4
8 VOUT
7 EN
LX
6 COMP
FB
5
VOUT
Rev. 2.0 October 2014
www.aosmd.com
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AOZ3046PI.PDF ] | |
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