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ISL12028A 데이터시트 PDF




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부품번호 ISL12028A 기능
기능 Real Time Clock/Calendar
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ISL12028A 데이터시트, 핀배열, 회로
Data Sheet
ISL12028, ISL12028A
August 14, 2015
FN8233.10
Real Time Clock/Calendar with I2C Bus™
and EEPROM
The ISL12028 device is a low power real time clock with
clock/calendar, power-fail indicator, clock output and crystal
compensation, two periodic or polled alarms (CMOS output),
intelligent battery backup switching, CPU Supervisor,
integrated 512x8-bit EEPROM configured in 16 bytes per
page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12028 and ISL12028A Power Control Settings are
different. The ISL12028 uses the Legacy Mode Setting, and
the ISL12028A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12028A. Please refer to “Power Control Operation” on
page 14 for more details. Also, please refer to “I2C
Communications During Battery Backup and LVR Operation”
on page 25 for important details.
Pinout
ISL12028, ISL12028A
(14 LD TSSOP, SOIC)
TOP VIEW
X1
X2
NC
NC
NC
RESET
GND
1
2
3
4
5
6
7
14 VDD
13 VBAT
12 IRQ/FOUT
11 NC
10 NC
9 SCL
8 SDA
NC = No internal connection
Features
• Real Time Clock/Calendar
- Tracks time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
- Power Failure Detection
- 800nA Battery Supply Current
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM:
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• CPU Supervisor Functions:
- Power On Reset, Low Voltage Sense
- Watchdog Timer (0.25s, 0.75s and 1.75s)
• I2C Interface
- 400kHz Data Transfer Rate
• 14 Ld SOIC and 14 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas LLC 2005, 2006, 2008, 2010, 2015.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.




ISL12028A pdf, 반도체, 판매, 대치품
ISL12028, ISL12028A
Absolute Maximum Ratings
Voltage on VDD, VBAT, SCL, SDA, RESET and IRQ/FOUT Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model (MIL-STD-883, Method 3014) . . . . . . .>±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>175V
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
14 Ld SOIC Package (Notes 5, 6) . . . .
90
40
14 Ld TSSOP Package (Note 5, 6) . . .
110
35
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is taken at the package top center.
DC Operating Characteristics
SYMBOL
PARAMETER
VDD
VBAT
Main Power Supply
Backup Power Supply
Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C
and VDD = 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C.
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNIT
NOTES
2.7 5.5 V
1.8 5.5 V
Electrical Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
IDD1 Supply Current with I2C Active
IDD2
IDD3
IBAT
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
IBATLKG Battery Input Leakage
VTRIP VBAT Mode Threshold
VTRIPHYS VTRIP Hysteresis
VBATHYS VBAT Hysteresis
VDD SR- VDD Negative Slew Rate
IRQ/FOUT OUTPUT
VOL Output Low Voltage
VOH Output High Voltage
CONDITIONS
VDD = 2.7V
VDD = 5.5V
VDD = 2.7V
VDD = 5.5V
VDD = VSDA = VSCL = 2.7V
VDD = VSDA = VSCL = 5.5V
VBAT = 1.8V,
VDD = VSDA = VSCL = VRESET = 0V
VBAT = 3.0V,
VDD = VSDA = VSCL = VRESET = 0V
VDD = 5.5V, VBAT = 1.8V
MIN
(Note 16)
1.8
VDD = 5.5V
IOL = 3mA
VDD = 2.7V
IOL = 1mA
VDD = 5.5V
IOL = -1.0mA
VDD = 2.7V
IOL = -0.4mA
VDD x 0.7
VDD x 0.7
TYP
800
850
2.2
30
50
MAX
(Note 16)
500
800
2.5
3.5
10
20
1000
1200
100
2.6
10
0.3*VDD
0.3*VDD
UNIT
µA
µA
mA
mA
µA
µA
nA
NOTES
7, 8, 9
7, 8, 9
9
7, 10, 11
nA
nA
V
mV
mV
V/ms
11
11, 13
11, 13
12
V
V
V
V
4 FN8233.10
August 14, 2015

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ISL12028A 전자부품, 판매, 대치품
Timing Diagrams
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
ISL12028, ISL12028A
tF
tSU:DAT
tHD:STA
tHIGH
tLOW
tR
tHD:DAT
tAA tDH
FIGURE 1. BUS TIMING
tHD:STO
tSU:STO
tBUF
SCL
SDA
8TH BIT OF LAST BYTE
ACK
STOP
CONDITION
FIGURE 2. WRITE CYCLE TIMING
tWC
START
CONDITION
SCL
SDA
tRSP
tRSP<tWDO
tRSP>tWDO
tRST
tRSP>tWDO
tRST
RESET
START
STOP START
Note: All inputs are ignored during the active reset period (tRST).
FIGURE 3. WATCHDOG TIMING
VDD
VRESET
tPURST
RESET
tR
7
tRPD
tPURST
FIGURE 4. RESET TIMING
tF
VRVALID
FN8233.10
August 14, 2015

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관련 데이터시트

부품번호상세설명 및 기능제조사
ISL12028

Real Time Clock/Calendar

Intersil Corporation
Intersil Corporation
ISL12028A

Real Time Clock/Calendar

Intersil
Intersil

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