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부품번호 MPC8309
기능 PowerQUICC II Pro Integrated Communications Processor Reference Manual
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MPC8309 데이터시트, 핀배열, 회로
MPC8309 PowerQUICC II Pro
Integrated Communications
Processor Reference Manual
MPC8309RM
Rev. 2
10/2014




MPC8309 pdf, 반도체, 판매, 대치품
Paragraph
Number
2.2
2.3
Contents
Title
Page
Number
Accessing IMMR Memory from the Local Processor..................................................... 2-1
IMMR Address Map ........................................................................................................ 2-1
Chapter 3
Signal Descriptions
3.1 Signals Overview ............................................................................................................. 3-1
3.2 Output Signal States During Reset ................................................................................ 3-20
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.5
4.5.1
4.5.2
Chapter 4
Reset, Clocking, and Initialization
External Signals ............................................................................................................... 4-1
Reset Signals................................................................................................................ 4-1
Clock Signals ............................................................................................................... 4-2
Functional Description..................................................................................................... 4-4
Reset Operations .......................................................................................................... 4-4
Power-On Reset Flow .................................................................................................. 4-6
Hard Reset Flow .......................................................................................................... 4-7
Reset Configuration ......................................................................................................... 4-8
Reset Configuration Signals ........................................................................................ 4-8
Reset Configuration Words........................................................................................ 4-10
Loading the Reset Configuration Words ................................................................... 4-17
Clocking ........................................................................................................................ 4-25
System Clock Domains.............................................................................................. 4-26
Memory Map/Register Definitions ................................................................................ 4-27
Reset Configuration Register Descriptions................................................................ 4-27
Clock Configuration Registers................................................................................... 4-31
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
Chapter 5
System Boot
Booting from On Chip ROM ........................................................................................... 5-1
eSDHC Boot .................................................................................................................... 5-1
Overview...................................................................................................................... 5-2
Features........................................................................................................................ 5-2
SD/MMC Card Data Structure .................................................................................... 5-3
eSDHC Controller Initial Configuration...................................................................... 5-7
eSDHC Controller Boot Sequence .............................................................................. 5-7
eSDHC Boot Error Handling....................................................................................... 5-8
SPI Boot ROM................................................................................................................. 5-9
MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2
ii Freescale Semiconductor

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MPC8309 전자부품, 판매, 대치품
Paragraph
Number
Contents
Title
Chapter 8
e300 Processor Core Overview
Page
Number
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.5
Overview.......................................................................................................................... 8-1
Features........................................................................................................................ 8-3
Instruction Unit ............................................................................................................ 8-6
Independent Execution Units....................................................................................... 8-7
Completion Unit .......................................................................................................... 8-8
Memory Subsystem Support........................................................................................ 8-8
Bus Interface Unit (BIU) ........................................................................................... 8-10
System Support Functions ......................................................................................... 8-11
e300 Processor and System Version Numbers............................................................... 8-13
PowerPC Architecture Implementation ......................................................................... 8-13
Implementation-Specific Information............................................................................ 8-14
Register Model........................................................................................................... 8-14
Instruction Set and Addressing Modes ...................................................................... 8-26
Cache Implementation ............................................................................................... 8-29
Interrupt Model .......................................................................................................... 8-31
Memory Management................................................................................................ 8-35
Instruction Timing ..................................................................................................... 8-36
Core Interface ............................................................................................................ 8-37
Debug Features ......................................................................................................... 8-39
Differences Between Cores........................................................................................... 8-40
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
Chapter 9
Integrated Programmable Interrupt Controller (IPIC)
Introduction...................................................................................................................... 9-1
Features ............................................................................................................................ 9-4
Modes of Operation ......................................................................................................... 9-4
Core Enable Mode ....................................................................................................... 9-4
Core Disable Mode ...................................................................................................... 9-4
External Signal Description ............................................................................................. 9-5
Overview...................................................................................................................... 9-5
Detailed Signal Descriptions ....................................................................................... 9-5
Memory Map/Register Definition ................................................................................... 9-5
System Global Interrupt Configuration Register (SICFR) .......................................... 9-7
System Global Interrupt Vector Register (SIVCR)...................................................... 9-8
System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 9-11
System Internal Interrupt Group A Priority Register (SIPRR_A)............................. 9-14
System Internal Interrupt Group B Priority Register (SIPRR_B) ............................. 9-15
MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2
Freescale Semiconductor
v

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