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PDF MPC8309 Data sheet ( Hoja de datos )
| Número de pieza | MPC8309 | |
| Descripción | PowerQUICC II Pro Integrated Communications Processor | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
Document Number:MPC8309EC
Rev 4, 12/2014
MPC8309
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
This document provides an overview of the MPC8309
PowerQUICC II Pro processor features. The MPC8309 is a
cost-effective, highly integrated communications processor
that addresses the requirements of several networking
applications, including residential gateways,
modem/routers, industrial control, and test and measurement
applications. The MPC8309 extends current PowerQUICC
offerings, adding higher CPU performance, additional
functionality, and faster interfaces, while addressing the
requirements related to time-to-market, price, power
consumption, and board real estate. This document describes
the electrical characteristics of MPC8309.
To locate published errata or updates for this document, refer
to the MPC8309 product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 22
9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14. eSDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15. FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
16. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
17. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
19. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
21. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
22. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 52
23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
25. System Design Information . . . . . . . . . . . . . . . . . . . 75
26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 78
27. Document Revision History . . . . . . . . . . . . . . . . . . . 80
© 2011, 2014 Freescale Semiconductor, Inc. All rights reserved.
1 page  
Overview
— Six groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Unique vector number for each interrupt source
• PCI interface
— Designed to comply with PCI Local Bus Specification, Revision 2.3
— 32-bit PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— Not 5-V compatible
— Support for host and agent modes
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting three masters on PCI
— Arbiter support for two-level priority request/grant signal pairs
— Support for accesses to all PCI address spaces
— Support for parity
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Mapping from an external 32-/64-bit address space to the internal 32-bit local space
— Support for dual address cycle (DAC) (as a target only)
— Internal configuration registers accessible from PCI
— Selectable snooping for inbound transactions
— Four outbound Translation Address Windows
– Support for mapping 32-bit internal local memory space to an external 32-bit PCI address
space and translating that address within the PCI space
— Four inbound Translation Address Windows corresponding to defined PCI BARs
– The first BAR is 32-bits and dedicated to on-chip register access
– The second BAR is 32-bits for general use
– The remaining two BARs may be 32- or 64-bits and are also for general use
• Enhanced secure digital host controller (eSDHC)
— Compatible with the SD Host Controller Standard Specification Version 2.0 with test event
register support
— Compatible with the MMC System Specification Version 4.2
— Compatible with the SD Memory Card Specification Version 2.0 and supports the high capacity
SD memory card
— Compatible with the SD Input/Output (SDIO) Card Specification, Version 2.0
— Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, and RS-MMC cards
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
5
5 Page 
Power Characteristics
V I/O Voltage (GVDD and OVDD)
Core Voltage (VDD)
90%
0.7 V
0
PORESET
t
>= 32 tSYS_CLK_IN / PCI_SYNC_IN
Figure 3. MPC8309 Power-Up Sequencing Example
3 Power Characteristics
The typical power dissipation for this family of MPC8309 devices is shown in the following table.
Table 5. MPC8309 Power Dissipation
Core
Frequency (MHz)
QUICC Engine
Frequency (MHz)
CSB
Frequency (MHz)
Typical
Maximum
Unit
Note
266
233
133
0.341
0.920
W 1, 2, 3
333
233
133
0.361
0.938
W 1, 2, 3
400
233
133
0.381
0.969
W 1,2,3
417
233
167
0.429
1.003
W 1,2,3
Notes:
1. The values do not include I/O supply power (OVDD and GVDD), but it does include VDD and AVDD power. For I/O power
values, see Table 6.
2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon.
3. Maximum power is based on a voltage of VDD = 1.05 V, WC process, a junction TJ = 105C, and a smoke test code.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MPC8309.PDF ] | |
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