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MPC8309 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MPC8309
기능 PowerQUICC II Pro Integrated Communications Processor
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MPC8309 데이터시트, 핀배열, 회로
Freescale Semiconductor
Technical Data
Document Number:MPC8309EC
Rev 4, 12/2014
MPC8309
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
This document provides an overview of the MPC8309
PowerQUICC II Pro processor features. The MPC8309 is a
cost-effective, highly integrated communications processor
that addresses the requirements of several networking
applications, including residential gateways,
modem/routers, industrial control, and test and measurement
applications. The MPC8309 extends current PowerQUICC
offerings, adding higher CPU performance, additional
functionality, and faster interfaces, while addressing the
requirements related to time-to-market, price, power
consumption, and board real estate. This document describes
the electrical characteristics of MPC8309.
To locate published errata or updates for this document, refer
to the MPC8309 product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 22
9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14. eSDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15. FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
16. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
17. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
19. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
21. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
22. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 52
23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
25. System Design Information . . . . . . . . . . . . . . . . . . . 75
26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 78
27. Document Revision History . . . . . . . . . . . . . . . . . . . 80
© 2011, 2014 Freescale Semiconductor, Inc. All rights reserved.




MPC8309 pdf, 반도체, 판매, 대치품
Overview
For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference
Manual with Protocol Interworking.
• DDR SDRAM memory controller
— Programmable timing supporting DDR2 SDRAM
— Integrated SDRAM clock generation
— Supports 8-bit ECC
— 16/32-bit data interface, up to 333-MHz data rate
— 14 address lines
— The following SDRAM configurations are supported:
– Up to two physical banks (chip selects), 512-Mbyte addressable space for 32 bit data
interface
– 64-Mbit to 2-Gbit devices with x8/x16/x32 data ports (no direct x4 support)
— One 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit devices or four 8-bit
devices on a 32-bit bus Support for up to 16 simultaneous open pages for DDR2
— Two clock pair to support up to 4 DRAM devices
— Supports auto refresh
— On-the-fly power management using CKE
• Enhanced local bus controller (eLBC)
— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz
— Eight chip selects supporting eight external slaves
– Four chip selects dedicated
– Four chip selects offered as multiplexed option
— Supports boot from parallel NOR Flash and parallel NAND Flash
— Supports programmable clock ratio dividers
— Up to eight-beat burst transfers
— 16- and 8-bit ports, separate LWE for each 8 bit
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– NAND Flash control machine (FCM)
— Variable memory block sizes for FCM, GPCM, and UPM mode
— Default boot ROM chip select with configurable bus width (8 or 16)
— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC
slave devices
• Integrated programmable interrupt controller (IPIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for external and internal discrete interrupt sources
— Programmable highest priority request
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
4 Freescale Semiconductor

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MPC8309 전자부품, 판매, 대치품
Electrical Characteristics
• IO Sequencer
• Direct memory access (DMA) controller (DMA Engine 2)
— Four independent fully programmable DMA channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Misaligned transfer capability for source/destination address
— Data chaining and direct mode
— Interrupt on completed segment, error, and chain
• DUART
— Supports 2 DUART
— Each has two 2-wire interfaces (RxD, TxD)
– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI)
— Master or slave support
• Power managemnt controller (PMC)
— Supports core doze/nap/sleep/ power management
— Exits low power state and returns to full-on mode when
– The core internal time base unit invokes a request to exit low power state
– The power management controller detects that the system is not idle and there are
outstanding transactions on the internal bus or an external interrupt.
• Parallel I/O
— General-purpose I/O (GPIO)
– 56 parallel I/O pins multiplexed on various chip interfaces
– Interrupt capability
• System timers
— Periodic interrupt timer
— Software watchdog timer
— Eight general-purpose timers
• Real time clock (RTC) module
— Maintains a one-second count, unique over a period of thousands of years
— Two possible clock sources:
– External RTC clock (RTC_PIT_CLK)
– CSB bus clock
• IEEE Std. 1149.1™ compliant JTAG boundary scan
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8309. The MPC8309 is currently targeted to these specifications. Some of these specifications are
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
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