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MK10DN32VFM5 데이터시트 PDF




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MK10DN32VFM5 데이터시트, 핀배열, 회로
K10 Sub-Family Reference Manual
Supports: MK10DN32VFM5, MK10DX32VFM5, MK10DN64VFM5,
MK10DX64VFM5, MK10DN128VFM5, MK10DX128VFM5
Document Number: K10P32M50SF0RM
Rev. 2, Feb 2012




MK10DN32VFM5 pdf, 반도체, 판매, 대치품
Section Number
Title
Page
3.2 Core modules................................................................................................................................................................57
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................57
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................59
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................64
3.2.4 JTAG Controller Configuration...................................................................................................................66
3.3 System modules............................................................................................................................................................66
3.3.1 SIM Configuration.......................................................................................................................................66
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................67
3.3.3 PMC Configuration......................................................................................................................................67
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................68
3.3.5 MCM Configuration....................................................................................................................................70
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................71
3.3.7 Peripheral Bridge Configuration..................................................................................................................73
3.3.8 DMA request multiplexer configuration......................................................................................................73
3.3.9 DMA Controller Configuration...................................................................................................................76
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................77
3.3.11 Watchdog Configuration..............................................................................................................................79
3.4 Clock Modules..............................................................................................................................................................80
3.4.1 MCG Configuration.....................................................................................................................................80
3.4.2 OSC Configuration......................................................................................................................................81
3.4.3 RTC OSC configuration...............................................................................................................................82
3.5 Memories and Memory Interfaces................................................................................................................................82
3.5.1 Flash Memory Configuration.......................................................................................................................82
3.5.2 Flash Memory Controller Configuration.....................................................................................................85
K10 Sub-Family Reference Manual, Rev. 2, Feb 2012
4 Freescale Semiconductor, Inc.

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MK10DN32VFM5 전자부품, 판매, 대치품
Section Number
Title
Page
6.2 Reset..............................................................................................................................................................................146
6.2.1 Power-on reset (POR)..................................................................................................................................146
6.2.2 System reset sources....................................................................................................................................146
6.2.3 MCU Resets.................................................................................................................................................150
6.2.4 Reset Pin .....................................................................................................................................................152
6.2.5 Debug resets.................................................................................................................................................152
6.3 Boot...............................................................................................................................................................................153
6.3.1 Boot sources.................................................................................................................................................153
6.3.2 Boot options.................................................................................................................................................153
6.3.3 FOPT boot options.......................................................................................................................................154
6.3.4 Boot sequence..............................................................................................................................................155
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................157
7.2 Power modes.................................................................................................................................................................157
7.3 Entering and exiting power modes...............................................................................................................................159
7.4 Power mode transitions.................................................................................................................................................160
7.5 Power modes shutdown sequencing.............................................................................................................................161
7.6 Module Operation in Low Power Modes......................................................................................................................162
7.7 Clock Gating.................................................................................................................................................................165
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................167
8.2 Flash Security...............................................................................................................................................................167
8.3 Security Interactions with other Modules.....................................................................................................................168
8.3.1 Security Interactions with EzPort................................................................................................................168
8.3.2 Security Interactions with Debug.................................................................................................................168
K10 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc.
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