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기능 Applications Processors
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IMX51 데이터시트, 핀배열, 회로
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX51CEC
Rev. 6, 10/2012
IMX51
i.MX51 Applications
Processors for Consumer and
Industrial Products
Package Information
Plastic Package
Case 2058 13 x 13 mm, 0.5 mm pitch
Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3 for ordering information.
1 Introduction
The i.MX51 multimedia applications processors
represent Freescale Semiconductor’s latest addition to a
growing family of multimedia-focused products that
offer high performance processing and are optimized for
lowest power consumption.
The i.MX51 processors feature Freescale’s advanced and
power-efficient implementation of the ARM
Cortex™-A8 core, which operates at speeds as high as
800 MHz. Up to 200 MHz DDR2 and mobile DDR
DRAM clock rates are supported. These devices are
suitable for applications such as the following:
• Netbooks (web tablets)
• Nettops (Internet desktop devices)
• Mobile Internet devices (MID)
• Portable media players (PMP)
• Portable navigation devices (PND)
• High-end PDAs
• Gaming consoles
• Automotive navigation and entertainment (see
automotive data sheet, IMX51AEC)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 12
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 14
3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 15
3.3. I2C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 15
3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 16
3.5. Wireless External Interface Module (WEIM) . . . . 16
3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 16
3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 16
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4. Output Buffer Impedance Characteristics . . . . . . 31
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 74
5. Package Information and Contact Assignments . . . . . 153
5.1. 13 x 13 mm Package Information . . . . . . . . . . . . 153
5.2. 19 x 19 mm Package Information . . . . . . . . . . . . 173
5.3. 13 × 13 mm, 0.5 Pitch Ball Map . . . . . . . . . . . . . 191
5.4. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 195
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
© 2012 Freescale Semiconductor, Inc. All rights reserved.




IMX51 pdf, 반도체, 판매, 대치품
Introduction
1.2 Block Diagram
Figure 1 shows the functional modules of the processor.
Digital
Audio
DDR
Memory
NOR/Nand Battery Ctrl USB
Camera 1 LCD Display 1
Flash
Device Dev/Host Camera 2 LCD Display 2
ATA HDD
External
Memory I/F
Smart DMA
(SDMA)
SPBA
SDMA Peripherals
eSDHC (4)
UART
SPDIF Tx
SSI
eCSPI (1 of 2)
SIM
FEC
P-ATA
Fuse Box
USB PHY
Application Processor Domain (AP)
TV Encoder
USB OTG +
3 HS Ports
Internal
RAM
(128 Kbytes)
Boot
ROM
Security
SAHARA
Lite
RTIC
SCC
SRTC
CSU
TZIC
T im ers
WDOG (2)
GPT
EPIT (2)
Image Processing
Subsystem
ARM Cortex A8
Platform
ARM Cortex A8
Neon and VFP
L1 I/D cache
L2 cache
ETM, CTI0,1
Video
Proc. Unit
(VPU)
3D Graphics
Proc Unit
(GPU)
Graphics
Memory
(128 Kbytes)
2D Graphics
Proc Unit
(GPU2D)
AP Peripherals
eCSPI (2)
CSPI
UART (3)
AUDMUX
I2C(2),HSI2C
1-WIRE
PWM (2)
IIM
IOMUXC
KPP
GPIOx32 (4)
SJC
SSI (3)
FIRI
Debug
DAP
TPIU
CTI (2)
Clock and Reset
PLL (3)
CCM
GPC
SRC
XTALOSC
CAMP (2)
JTAG
IrDA
XVR
Bluetooth
WLAN
U SB -OT G
XVR
MMC/SDIO
Keypad
Access.
Conn.
Figure 1. Functional Block Diagram
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
4 Freescale Semiconductor

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IMX51 전자부품, 판매, 대치품
Features
Table 2. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name Subsystem
Brief Description
eSDHC-4
(muxed with
P-ATA)
Enhanced
Multi-Media
Card/
Secure Digital
Host
Controller
Connectivity
Peripherals
Can be configured as eSDHC (see above) and is muxed with the P-ATA
interface.
FEC
FIRI
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPT
GPU
GPU2D
I2C-1
I2C-2
HS-I2C
Fast Ethernet Connectivity
Controller
Peripherals
Fast
Infra-Red
Interface
General
Purpose I/O
Modules
Connectivity
Peripherals
System
Control
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support both
10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media.
Fast Infra-Red Interface
These modules are used for general purpose input/output to external ICs. Each
GPIO module supports up to 32 bits of I/O.
General
Purpose
Timer
Timer
Peripherals
Graphics
Processing
Unit
Multimedia
Peripherals
Graphics
Multimedia
Processing Peripherals
Unit-2D Ver. 1
I2C Interface Connectivity
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event, and can be configured to trigger
a capture event on either the leading or trailing edges of an input pulse. When
the timer is configured to operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with minimal processor
intervention. The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on an external
clock or on an internal clock.
The GPU provides hardware acceleration for 2D and 3D graphics
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720
resolution. It supports color representation up to 32 bits per pixel.
The GPU with its 128 KByte memory enables high performance mobile 3D and
2D vector graphics at rates up to 27 Mtriangles/sec, 166 Mpixels/sec,
664 Mpixels/sec (Z).
The GPU2D provides hardware acceleration for 2D graphic
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720 resolution.
I2C provides serial interface for controlling peripheral devices. Data rates of up
to 400 Kbps are supported by two of the I2C ports. Data rates of up to 3.4 Mbps
(I2C Specification v2.1) are supported by the HS-I2C.
Note: See the errata for the HS-I2C in the i.MX51 Chip Errata. The two standard
I2C modules have no errata.
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
7

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