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LM4F230H5QR 데이터시트 PDF




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LM4F230H5QR 데이터시트, 핀배열, 회로
TEXAS INSTRUMENTS-ADVANCE INFORMATION
Stellaris® LM4F230H5QR Microcontroller
DATA SHEET
DS-LM4F230H5QR-14007.2601
SPMS314E
Copyright © 2007-2013
Te xa s In stru me n ts In co rporated




LM4F230H5QR pdf, 반도체, 판매, 대치품
Table of Contents
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7
2.7.1
2.7.2
2.8
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.3
3.4
3.5
3.6
3.7
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
Vector Table ................................................................................................................ 109
Exception Priorities ...................................................................................................... 110
Interrupt Priority Grouping ............................................................................................ 111
Exception Entry and Return ......................................................................................... 111
Fault Handling ............................................................................................................. 114
Fault Types ................................................................................................................. 115
Fault Escalation and Hard Faults .................................................................................. 115
Fault Status Registers and Fault Address Registers ...................................................... 116
Lockup ....................................................................................................................... 116
Power Management .................................................................................................... 117
Entering Sleep Modes ................................................................................................. 117
Wake Up from Sleep Mode .......................................................................................... 117
Instruction Set Summary .............................................................................................. 118
Cortex-M4 Peripherals ......................................................................................... 125
Functional Description ................................................................................................. 125
System Timer (SysTick) ............................................................................................... 126
Nested Vectored Interrupt Controller (NVIC) .................................................................. 127
System Control Block (SCB) ........................................................................................ 128
Memory Protection Unit (MPU) ..................................................................................... 128
Floating-Point Unit (FPU) ............................................................................................. 133
Register Map .............................................................................................................. 137
System Timer (SysTick) Register Descriptions .............................................................. 140
NVIC Register Descriptions .......................................................................................... 144
System Control Block (SCB) Register Descriptions ........................................................ 159
Memory Protection Unit (MPU) Register Descriptions .................................................... 188
Floating-Point Unit (FPU) Register Descriptions ............................................................ 197
JTAG Interface ...................................................................................................... 203
Block Diagram ............................................................................................................ 204
Signal Description ....................................................................................................... 204
Functional Description ................................................................................................. 205
JTAG Interface Pins ..................................................................................................... 205
JTAG TAP Controller ................................................................................................... 207
Shift Registers ............................................................................................................ 207
Operational Considerations .......................................................................................... 208
Initialization and Configuration ..................................................................................... 210
Register Descriptions .................................................................................................. 210
Instruction Register (IR) ............................................................................................... 211
Data Registers ............................................................................................................ 213
System Control ..................................................................................................... 215
Signal Description ....................................................................................................... 215
Functional Description ................................................................................................. 215
Device Identification .................................................................................................... 215
Reset Control .............................................................................................................. 216
Non-Maskable Interrupt ............................................................................................... 221
Power Control ............................................................................................................. 221
Clock Control .............................................................................................................. 222
System Control ........................................................................................................... 230
Initialization and Configuration ..................................................................................... 232
4 January 19, 2013
Texas Instruments-Advance Information

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LM4F230H5QR 전자부품, 판매, 대치품
Stellaris® LM4F230H5QR Microcontroller
12 Watchdog Timers ................................................................................................. 758
12.1 Block Diagram ............................................................................................................ 759
12.2 Functional Description ................................................................................................. 759
12.2.1 Register Access Timing ............................................................................................... 760
12.3 Initialization and Configuration ..................................................................................... 760
12.4 Register Map .............................................................................................................. 760
12.5 Register Descriptions .................................................................................................. 761
13 Analog-to-Digital Converter (ADC) ..................................................................... 783
13.1 Block Diagram ............................................................................................................ 784
13.2 Signal Description ....................................................................................................... 785
13.3 Functional Description ................................................................................................. 786
13.3.1 Sample Sequencers .................................................................................................... 786
13.3.2 Module Control ............................................................................................................ 787
13.3.3 Hardware Sample Averaging Circuit ............................................................................. 790
13.3.4 Analog-to-Digital Converter .......................................................................................... 791
13.3.5 Differential Sampling ................................................................................................... 794
13.3.6 Internal Temperature Sensor ........................................................................................ 796
13.3.7 Digital Comparator Unit ............................................................................................... 797
13.4 Initialization and Configuration ..................................................................................... 801
13.4.1 Module Initialization ..................................................................................................... 801
13.4.2 Sample Sequencer Configuration ................................................................................. 802
13.5 Register Map .............................................................................................................. 802
13.6 Register Descriptions .................................................................................................. 804
14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 877
14.1 Block Diagram ............................................................................................................ 878
14.2 Signal Description ....................................................................................................... 878
14.3 Functional Description ................................................................................................. 879
14.3.1 Transmit/Receive Logic ............................................................................................... 879
14.3.2 Baud-Rate Generation ................................................................................................. 880
14.3.3 Data Transmission ...................................................................................................... 881
14.3.4 Serial IR (SIR) ............................................................................................................. 881
14.3.5 ISO 7816 Support ....................................................................................................... 882
14.3.6 Modem Handshake Support ......................................................................................... 883
14.3.7 LIN Support ................................................................................................................ 884
14.3.8 9-Bit UART Mode ........................................................................................................ 885
14.3.9 FIFO Operation ........................................................................................................... 885
14.3.10 Interrupts .................................................................................................................... 886
14.3.11 Loopback Operation .................................................................................................... 887
14.3.12 DMA Operation ........................................................................................................... 887
14.4 Initialization and Configuration ..................................................................................... 887
14.5 Register Map .............................................................................................................. 889
14.6 Register Descriptions .................................................................................................. 890
15 Synchronous Serial Interface (SSI) .................................................................... 940
15.1 Block Diagram ............................................................................................................ 941
15.2 Signal Description ....................................................................................................... 941
15.3 Functional Description ................................................................................................. 942
15.3.1 Bit Rate Generation ..................................................................................................... 942
15.3.2 FIFO Operation ........................................................................................................... 943
January 19, 2013
Texas Instruments-Advance Information
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LM4F230H5QR

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