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ATxmega256A3B PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ATxmega256A3B
기능 Microcontroller
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ATxmega256A3B 데이터시트, 핀배열, 회로
Features
High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller
Non-volatile Program and Data Memories
– 256 KB of In-System Self-Programmable Flash
– 8 KB Boot Code Section with Independent Lock Bits
– 4 KB EEPROM
– 16 KB Internal SRAM
Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High-Resolution Extension on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Six USARTs
IrDA modulation/demodulation for one USART
– Two Two-Wire Interfaces with dual address match (I2C and SMBus compatible)
– Two SPI (Serial Peripheral Interface) peripherals
– AES and DES Crypto Engine
– 32-bit Real Time Counter with separate Oscillator and Battery Backup System
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converters
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) for programming and debugging
I/O and Packages
– 49 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN/MLF
Operating Voltage
– 1.6 – 3.6V
Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
8/16-bit
XMEGA A3B
Microcontroller
ATxmega256A3B
Preliminary
Not recommended for
new designs - Use
ATxmega256A3BU
Typical Applications
Industrial control
Factory automation
Climate control
ZigBee
Building control
Motor control
Board control
Networking
White Goods
Optical
Hand-held battery applications
Power tools
HVAC
Metering
Medical Applications
8116J–AVR–06/2013
Not recommended for new designs -
Use ATxmega256A3BU




ATxmega256A3B pdf, 반도체, 판매, 대치품
XMEGA A3B
3. Overview
The XMEGAA3B is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR® enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the XMEGA A3B achieves throughputs approaching 1 Million
Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conven-
tional single-accumulator or CISC based microcontrollers.
The XMEGA A3B devices provides the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 49 general purpose
I/O lines, 32-bit Real Time Counter (RTC) with Battery Backup System, seven flexible 16-bit
Timer/Counters with compare modes and PWM, six USARTs, two Two Wire Serial Interfaces
(TWIs), two Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, two 8-channel, 12-
bit ADCs with optional differential input with programmable gain, one 2-channel 12-bit DAC, four
analog comparators with window mode, programmable Watchdog Timer with separate Internal
Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out
Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
The XMEGA A3B devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consump-
tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock to each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-
gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download the application program to the Flash
memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-
cation Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3B is a pow-
erful microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
8116J–AVR–06/2013
Not recommended for new designs -
Use ATxmega256A3BU
4

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ATxmega256A3B 전자부품, 판매, 대치품
XMEGA A3B
6. AVR CPU
6.1 Features
6.2 Overview
8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in SRAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M Bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
The XMEGA A3B uses the 8/16-bit AVR CPU. The main function of the CPU is program execu-
tion. The CPU must therefore be able to access memories, perform calculations and control
peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 7 shows
the CPU block diagram.
Figure 6-1. CPU block diagram
DATA BUS
Program
Counter
OCD
Flash
Program
Memory
Instruction
Register
32 x 8 General
Purpose
Registers
STATUS/
CONTROL
Instruction
Decode
8116J–AVR–06/2013
ALU
Multiplier/
DES
Peripheral
Module 1
Peripheral
Module 2
DATA BUS
SRAM
EEPROM
PMIC
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This
Not recommended for new designs -
Use ATxmega256A3BU
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부품번호상세설명 및 기능제조사
ATXMEGA256A3

(ATXMEGAxxxA3) 8/16-bit XMEGA A3 Microcontroller

ATMEL Corporation
ATMEL Corporation
ATxmega256A3B

Microcontroller

Atmel
Atmel

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