|
|
PDF ATxmega256A3B Data sheet ( Hoja de datos )
| Número de pieza | ATxmega256A3B | |
| Descripción | Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ATxmega256A3B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Features
• High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller
• Non-volatile Program and Data Memories
– 256 KB of In-System Self-Programmable Flash
– 8 KB Boot Code Section with Independent Lock Bits
– 4 KB EEPROM
– 16 KB Internal SRAM
• Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High-Resolution Extension on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Six USARTs
IrDA modulation/demodulation for one USART
– Two Two-Wire Interfaces with dual address match (I2C and SMBus compatible)
– Two SPI (Serial Peripheral Interface) peripherals
– AES and DES Crypto Engine
– 32-bit Real Time Counter with separate Oscillator and Battery Backup System
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converters
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) for programming and debugging
• I/O and Packages
– 49 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN/MLF
• Operating Voltage
– 1.6 – 3.6V
• Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
8/16-bit
XMEGA A3B
Microcontroller
ATxmega256A3B
Preliminary
Not recommended for
new designs - Use
ATxmega256A3BU
Typical Applications
• Industrial control
• Factory automation
• Climate control
• ZigBee
• Building control
• Motor control
• Board control
• Networking
• White Goods
• Optical
• Hand-held battery applications
• Power tools
• HVAC
• Metering
• Medical Applications
8116J–AVR–06/2013
Not recommended for new designs -
Use ATxmega256A3BU
1 page  
XMEGA A3B
The XMEGA A3B devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
3.1 Block Diagram
Figure 3-1. XMEGA A3B Block Diagram
PR[0..1]
XTAL1
XTAL2
PA[0..7]
PB[0..7]/
JTAG
PORT A (8)
ACA
ADCA
AREFA
VCC/10
Int. Ref.
Tempref
AREFB
ADCB
ACB
PORT B (8)
DACB
IRCOM
Event System
Controller
DMA
Controller
BUS
Controller
Oscillator
Circuits/
Clock
Generation
DATA BUS
SRAM
Oscillator
Control
Sleep
Controller
Prog/Debug
Controller
DES
AES
CPU
NVM Controller
Flash
OCD
Interrupt
Controller
EEPROM
Watchdog
Oscillator
Watchdog
Timer
Power
Supervision
POR/BOD &
RESET
PDI
JTAG
PORT B
USARTF0
TCF0
PORT C (8)
PC[0..7]
DATA BUS
EVENT ROUTING NETWORK
PORT D (8)
PD[0..7]
PORT E (6)
PE[0..5]
Real Time
Counter
Battery
Backup
Controller
32.768 kHz
XOSC
VBAT
Power
Supervision
TOSC1
TOSC2
VCC
GND
RESET/
PDI_CLK
PDI_DATA
PF[0..4,6..7]
VBAT
8116J–AVR–06/2013
Not recommended for new designs -
Use ATxmega256A3BU
5
5 Page 
Figure 7-2. Data Memory Map (Hexadecimal address)
1000
1FFF
EEPROM
(4 KB)
2000
5FFF
Internal SRAM
(16 KB)
XMEGA A3B
7.4.1
7.4.2
7.4.3
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3B is shown in the
”Peripheral Module Address Map” on page 57.
SRAM Data Memory
The XMEGA A3B devices have internal SRAM memory for data storage.
EEPROM Data Memory
The XMEGA A3B devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
8116J–AVR–06/2013
Not recommended for new designs -
Use ATxmega256A3BU
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATxmega256A3B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ATXMEGA256A3 | (ATXMEGAxxxA3) 8/16-bit XMEGA A3 Microcontroller | ATMEL Corporation |
| ATxmega256A3B | Microcontroller | ATMEL Corporation |
| ATxmega256A3BU | 8/16-bit Atmel XMEGA A3BUMicrocontroller | ATMEL Corporation |
| ATXMEGA256A3U | 8/16-bit Atmel XMEGA A3U Microcontroller | ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |