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MK30DN512ZVMD10 데이터시트 PDF




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MK30DN512ZVMD10 데이터시트, 핀배열, 회로
K30 Sub-Family Reference Manual
Supports: MK30DX128ZVLQ10, MK30DX128ZVMD10,
MK30DX256ZVLQ10, MK30DX256ZVMD10, MK30DN512ZVLQ10,
MK30DN512ZVMD10
Document Number: K30P144M100SF2RM
Rev. 6, Nov 2011




MK30DN512ZVMD10 pdf, 반도체, 판매, 대치품
Section Number
Title
Page
3.2 Core modules................................................................................................................................................................65
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................68
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................74
3.2.4 JTAG Controller Configuration...................................................................................................................75
3.3 System modules............................................................................................................................................................76
3.3.1 SIM Configuration.......................................................................................................................................76
3.3.2 Mode Controller Configuration...................................................................................................................77
3.3.3 PMC Configuration......................................................................................................................................77
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................78
3.3.5 MCM Configuration....................................................................................................................................80
3.3.6 Crossbar Switch Configuration....................................................................................................................80
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................82
3.3.8 Peripheral Bridge Configuration..................................................................................................................85
3.3.9 DMA request multiplexer configuration......................................................................................................87
3.3.10 DMA Controller Configuration...................................................................................................................90
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................91
3.3.12 Watchdog Configuration..............................................................................................................................92
3.4 Clock Modules..............................................................................................................................................................93
3.4.1 MCG Configuration.....................................................................................................................................93
3.4.2 OSC Configuration......................................................................................................................................94
3.4.3 RTC OSC configuration...............................................................................................................................95
3.5 Memories and Memory Interfaces................................................................................................................................95
3.5.1 Flash Memory Configuration.......................................................................................................................95
3.5.2 Flash Memory Controller Configuration.....................................................................................................99
3.5.3 SRAM Configuration...................................................................................................................................101
3.5.4 SRAM Controller Configuration.................................................................................................................104
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
4 Freescale Semiconductor, Inc.

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MK30DN512ZVMD10 전자부품, 판매, 대치품
Section Number
Title
Page
4.3 Flash Memory Map.......................................................................................................................................................155
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................156
4.4 SRAM memory map.....................................................................................................................................................157
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................157
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................157
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................161
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................166
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................167
5.2 Programming model......................................................................................................................................................167
5.3 High-Level device clocking diagram............................................................................................................................167
5.4 Clock definitions...........................................................................................................................................................168
5.4.1 Device clock summary.................................................................................................................................169
5.5 Internal clocking requirements.....................................................................................................................................171
5.5.1 Clock divider values after reset....................................................................................................................172
5.5.2 VLPR mode clocking...................................................................................................................................172
5.6 Clock Gating.................................................................................................................................................................172
5.7 Module clocks...............................................................................................................................................................173
5.7.1 PMC 1-kHz LPO clock................................................................................................................................174
5.7.2 WDOG clocking..........................................................................................................................................174
5.7.3 Debug trace clock.........................................................................................................................................175
5.7.4 PORT digital filter clocking.........................................................................................................................175
5.7.5 LPTMR clocking..........................................................................................................................................176
5.7.6 FlexCAN clocking.......................................................................................................................................176
5.7.7 UART clocking............................................................................................................................................177
5.7.8 SDHC clocking............................................................................................................................................177
5.7.9 I2S clocking.................................................................................................................................................177
5.7.10 TSI clocking.................................................................................................................................................178
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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부품번호상세설명 및 기능제조사
MK30DN512ZVMD10

K30 MCU

Freescale Semiconductor
Freescale Semiconductor

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